AETINA CONFIDENTIAL
UM-M3N1060-MN-v05
- 25 -
7. System Requirements
7.1 Power Sequencing
There is no power sequencing requirement for the input voltages to the MXM
module. However, the
PWR_EN
signal may be asserted only after all power rails are
within specified tolerance. The state of
PWR_GOOD
is undefined until all rails are
fully ramped.
Figure 7.1: Power sequencing
No voltage shall be applied to any MXM module signal pin (except power pins and
open drain signal specified in Table 7.1) until
PWR_GOOD
is asserted.
Table 7.1: Signals Exempted from Gating Requirement
Group
Signals
Power and Thermal
SMB_CLK, SMB_DAT, TH_OVER#,
TH_ALERT#, PWR_GOOD
System Management
WAKE#, PEX_CLK_REQ#
Display
DP_x_HPD
Summary of Contents for GeForce GTX 1060
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