92
State/Timing Modules Specifications and
Characteristics
Agilent Technologies 16715A, 16716A, 16717A, 16740A, 16741A, 16742A,
16750A, 16751A, 16752A Supplemental Specifications* and Characteristics (continued)
State Mode
16715A, 16716A, 16717A
16750A, 16751A, 16752A
167 Mb/s State Mode
400 Mb/s State Mode
Maximum state acquisition rate
333 Mb/s
400 Mb/s
on each channel
Channel count
(Number of modules x 68) - 34
(Number of modules x 68) - 34
Maximum channels on a single
306
306
time base and trigger
Number of independent analyzers
1, when 333 MHz state mode is selected
1, when 400 MHz state mode is selected
the second analyzer is turned off
the second analyzer is turned off
Minimum master to master clock time* [1]
3.003 ns
2.5 ns
Setup/hold time* [1]
2.5 ns window adjustable from 4.5/-2.0 ns to
2.5 ns window adjustable from 4.5/-2.0 ns to
(single-clock, single-edge)
-2.0/4.5 ns in 100 ps increments per channel
-2.0/4.5 ns in 100 ps increments per channel
Setup/hold time* [1]
3.0 ns window adjustable from 5.0/-2.0 ns to
3.0 ns window adjustable from 5.0/-2.0 ns to
(single-clock, multi-edge)
-1.5/4.5 ns in 100 ps increments per channel
-1.5/4.5 ns in 100 ps increments per channel
Setup/hold time (on individual channels
1.25 ns window
1.25 ns window
after running eye finder)
Minimum state clock pulse width
1.2 ns
1.2 ns
Time tag resolution [2]
4 ns
4 ns
Maximum time count between states
17 seconds
17 seconds
Number of state clocks
1
1
Maximum memory depth
16717A: 2M
16750A: 4M
16751A: 16M
16752A: 32M
Maximum trigger sequence speed
333 MHz
400 MHz
Maximum trigger sequence levels
15
15
Trigger sequence level branching
Dedicated next state branch or reset
Dedicated next state branch or reset
Trigger position
Start, center, end, or user defined
Start, center, end, or user defined
* All specifications noted by an asterisk are the performance standards against which the product is tested.
[1] Tested at input signal VH=-0.9V, VL=-1.7V, Slew rate=1V/ns, and threshold=-1.3V.
[2] Time or state tags halve the acquisition memory when there are no unassigned pods.
