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Chapter 8: Theory of Operation
Probes.
The 16910A logic analyzer card contains 6 probe pods; the 16911A
contains 4 probe pods. Each pod is comprised of one cable and contains 16
single-ended data channels, a clock channel, two serial I2C programming lines for
configuring analysis probes, +5 V for powering analysis probes, and 22 ground
signals. Each cable has a 40-pin probe cable connector.
The pods p5 Vdc ±5% auxiliary power to each 40-pin probe cable
connector. Each connector can deliver up to 300 mA with a maximum of 1.0 A
total from the analyzer card. A current limiting circuit protects the +5 V cable
power from current overload. The VCC_Enable signal is used to control power to
an analysis probe. Currently, the +5 Vdc is only disabled during the I2C self-test.
A variety of single-ended probes can be connected to the logic analyzer cables.
Comparators.
The comparators are single-ended devices that interpret
incoming data and clock signals as either high or low. A threshold voltage
provided by a digital-to-analog-converter (DAC) is coupled to the reference input
of the comparator through a precision resistor. Pod thresholds are individually
adjustable; clock and data share the same threshold. The comparator outputs
drive the acquisition ICs and clock divider circuitry.
Acquisition IC.
Each Acquisition IC processes 32 channels of data and 2
channels of clock information. The Acquisition ICs perform data sampling,
sequencing, store qualification, pattern recognition, and counting functions.
State or Timing sample clocks are sent from the Master card to the Acquisition
ICs in each of the Expander cards in a multi-card module. Sampled data is
decelerated and passed to the Memory Controller for storage in the Acquisition
Memory RAM array.
The Acquisition ICs also contain the 4 GHz sample Timing Zoom circuitry and
memory.
Memory Controller and Acquisition Memory.
The Memory Controllers store
data from the Acquisition ICs into the Acquisition Memory array which is
composed of 256 Mbit DDR DRAMs. They also unload data from the memory
array after an acquisition is complete, and they deliver the data to the mainframe
display system through the mainframe interface connector. In addition they
control refresh of the RAM array and can perform a search of stored data.
Master/Expander Connectors.
Connectors J9 through J13 and J15 route state
and timing clocks, calibration signals, data search signals, and control from the
Master card to all cards in the module.
Connectors J20 through J23 route pattern recognition signals between all cards
in a card set as well as control clocks from the Master card to other cards in the
set.
Mainframe Interface and Control FPGA.
The Mainframe interface consists
of an FPGA and the Mainframe Interface Connector. The connector brings power
Summary of Contents for 16900 Series
Page 3: ...3 Chapter The 16910A Logic Analyzer The 16911A Logic Analyzer...
Page 8: ...8 Contents...
Page 14: ...14 Chapter 1 General Information...
Page 18: ...18 Chapter 2 Preparing for Use...
Page 61: ...61 4 Calibrating This chapter gives you instructions for calibrating the logic analyzer...
Page 65: ...65 Chapter 5 Troubleshooting Troubleshooting Flowchart 1...
Page 66: ...66 Chapter 5 Troubleshooting Troubleshooting Flowchart 2...
Page 82: ...82 Chapter 5 Troubleshooting To test the cables 18 Return to the troubleshooting flow chart...
Page 94: ...94 Chapter 7 Replaceable Parts 16910A Exploded View Exploded view of the 16910A logic analyzer...
Page 95: ...95 Chapter 7 Replaceable Parts 16911A Exploded View Exploded view of the 16911A logic analyzer...
Page 96: ...96 Chapter 7 Replaceable Parts...
Page 102: ...102 Index...
