Figures
1-1.
P
ower
Cable
Supplied
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1-11
1-2.
V
oltage
Selector
and
Fuse
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1-12
1-3.
Connecting
16338A
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1-19
3-1.
Front
P
anel
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3-2
3-2.
T
est
Level
and
Measurement
Range
Setup
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3-4
3-3.
Source
Delay
and
Trigger
Delay
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3-7
3-4.
Rear
P
anel
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3-14
3-5.
Required
External
Trigger
Pulse
Specication
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3-14
3-6.
Pin
Assignment
F
or
Handler
Interface
Connector
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3-16
3-7.
Timing
Diagram
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3-18
3-8.
Denition
of
Impedance
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.
3-20
3-9.
V
ector
Representation
of
Impedance
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3-20
3-10.
Relationship
between
Measurement
P
arameters
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.
3-21
3-11.
Simplied
Model
of
4338B
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3-22
4-1.
Simple
Program
Example
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4-4
4-2.
SRQ
generation
sequence
(when
measurement
nishes)
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4-11
4-3.
Detecting
the
completion
of
measurement
using
SRQ
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4-12
4-4.
Reading
out
the
measured
result
in
ASCII
transfer
format
by
using
the
*TRG
command
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4-15
4-5.
Reading
out
the
measured
result
in
binary
transfer
format
using
*TRG
command
4-17
4-6.
Reading
out
the
measured
result
in
ASCII
transfer
format
using
the
:FETC?
command
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4-19
4-7.
Reading
out
measured
result
in
binary
transfer
format
using
:FETC?
command
4-21
5-1.
Proper
Use
of
the
Colon
and
Semicolon
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5-4
5-2.
Status
Reporting
Structure
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5-34
5-3.
Status
byte
Register
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5-35
5-4.
Standard
Event
Status
Register
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5-36
5-5.
Standard
Operation
Status
Group
Structure
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5-37
5-6.
Trigger
System
Conguration
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5-39
5-7.
Inside
an
Event
Detection
State
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.
5-40
5-8.
NR1
F
ormat
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5-41
5-9.
NR2
F
ormat
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5-41
5-10.
NR3
F
ormat
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5-41
5-11.
Real
Data
F
ormat
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5-42
6-1.
Measuring
Contact
Resistance
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6-4
6-2.
Measuring
Internal
Resistance
of
Batteries
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6-5
6-3.
Application
Sample
Program
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6-7
7-1.
SHORT
Correction
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7-1
7-2.
T
est
Lead
Extension
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.
7-3
9-1.
T
est
Signal
Frequency
A
ccuracy
T
est
Setup
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9-4
9-2.
Resistance
Measurement
A
ccuracy
T
est
Setup
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9-7
9-3.
T
est
Signal
Level
Functional
T
est
Setup
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9-12
9-4.
Handler
Interface
Functional
T
est
Setup
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9-14
9-5.
Handler
interface
Output
Order
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9-15
A
-1.
Serial
Number
Plate
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A
-3
B-1.
Handler
Interface
Comparison
Output
Signals
Diagram
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B-2
Contents-9
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Summary of Contents for 4338B
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