A5
Synthesizer
The
A5
synthesizer
provides
a
40
MHz
reference
frequency
,
a
20
MHz
CAL
OUT
signal,
an
INT
REF
signal,
a
FRA
C
N
OSC
signal,
a
STEP
OSC
signal,
and
a
520
MHz
signal.
The
40
MHz
reference
signal
is
supplied
to
the
A3A1
ALC
and
the
A6
receiver
IF
and
is
used
as
the
reference
signal.
The
FRA
C
N
OSC
and
the
STEP
OSC
signals
are
supplied
to
the
A4A1
1st
LO
and
are
used
to
generate
the
1st
local
oscillator
signal.
The
520
MHz
signal
is
supplied
to
the
A3A2
2nd
LO
and
is
used
to
generate
the
second
local
oscillator
signal.
The
A5
Synthesizer
consists
of
the
following
circuits:
REF
OSC
(Reference
Oscillator)
Leveler
FRA
C
N
OSC
(Fractional
N
Oscillator)
STEP
OSC
(Step
Oscillator)
X
13
Multiplier
REF
OSC
The
REF
OSC
generates
three
stable
reference
frequencies
of
40
MHz,
20
MHz,
and
10
MHz.
It
does
this
by
dividing
the
output
of
a
40
MHz
V
CXO
(voltage
control
crystal
oscillator)
as
required.
The
40
MHz
reference
signal
is
supplied
to
the
A3A1
ALC.
The
20
MHz
reference
frequency
goes
to
the
CAL
OUT
connector
on
the
front
panel
(through
the
leveler).
The
10
MHz
reference
frequency
is
routed
to
the
INT
REF
Output
connector
on
the
rear
panel.
When
a
10
MHz
external
reference
signal
is
applied
to
the
EXT
REF
Input
connector
on
the
rear
panel,
the
REF
OSC
output
signals
are
phase
locked
to
the
external
reference
signal.
The
REF
OSC
is
a
phase
locked
oscillator
and
contains
a
40
MHz
V
CXO
,
a
phase
detector
,
and
three
1/2
dividers
.
See
Figure
11-8.
When
the
10
MHz
external
reference
signal
is
applied
to
the
EXT
REF
Input
connector
on
the
rear
panel,
the
reference
frequency
is
divided
by
two
.
It
is
then
compared
with
the
V
CXO
frequency
(F
vcxo
)
divided
by
eight
in
the
phase
detector
.
Phase
locking
imposes
the
condition
of
10
MHz/2
=
F
vcxo
/8.
Therefore
,
the
output
frequency
(F
vcxo
)
is
locked
to
40
MHz.
A
detector
circuit
detects
the
external
reference
input
signal
and
sends
the
status
to
the
A1
CPU
.
Then
the
A1
CPU
displays
a
message
(ExtRef)
on
the
CRT
.
In
addition,
an
unlock
detector
monitors
the
control
voltage
to
the
V
CXO
.
When
the
control
voltage
is
out
of
limits
,
the
detector
sends
the
status
to
the
A1
CPU
.
Then
the
A1
CPU
causes
the
message
CA
UTION:
PHASE
LOCK
LOOP
UNLOCKED
to
be
displayed.
The
40
MHz
R
eference
Oscillator
Frequency
A
djustment
adjusts
the
V
CXO
to
lock
to
the
40
MHz
when
the
external
reference
signal
is
not
applied.
Leveler
The
leveler
is
a
power
amplier
that
produces
a
power
level
of
20
dBm
6
0.4
dB
.
The
front-panel
CAL
OUT
signal
is
derived
from
the
20
MHz
reference
signal
from
the
REF
OSC
through
the
leveler
.
The
CAL
OUT
Level
A
djustment
adjusts
the
leveler
to
output
a
CAL
OUT
signal
at
the
specied
power
level.
FRA
C
N
OSC
The
FRA
C
N
OSC
(Fractional
N
Oscillator)
generates
a
swept
signal
of
31.25
MHz
to
62.5
MHz
with
a
high
frequency
resolution.
The
signal
is
supplied
to
the
A4A1
1st
LO
and
is
used
to
generate
the
swept
1st
local
oscillator
signal.
11-16
Theory
of
Operation
Summary of Contents for Agilent 4396B
Page 10: ......
Page 32: ......
Page 43: ...Figure 2 7 CAL OUT Level Adjustment Location Adjustments and Correction Constants 2 11 ...
Page 46: ...Figure 2 10 Comb Generator Output 2 14 Adjustments and Correction Constants ...
Page 62: ...Figure 2 26 Final Gain Adjustment Location 2 30 Adjustments and Correction Constants ...
Page 76: ...Figure 3 1 Troubleshooting Organization 3 2 T roubleshooting ...
Page 84: ......
Page 90: ...Figure 5 1 Power Supply Lines Simpli ed Block Diagram 5 2 Power Supply T roubleshooting ...
Page 107: ...Figure 5 12 Power Supply Block Diagram 1 Power Supply T roubleshooting 5 19 ...
Page 108: ...Figure 5 13 Power Supply Block Diagram 2 5 20 Power Supply T roubleshooting ...
Page 109: ...Figure 5 14 Power Supply Block Diagram 3 Power Supply T roubleshooting 5 21 ...
Page 110: ......
Page 112: ...Figure 6 1 Digital Control Group Simpli ed Block Diagram 6 2 Digital Control T roubleshooting ...
Page 124: ......
Page 126: ...Figure 7 1 Source Group Block Diagram 7 2 Source Group T roubleshooting ...
Page 160: ...Figure 8 1 Receiver Group Simpli ed Block Diagram 8 2 Receiver Group T roubleshooting ...
Page 168: ......
Page 184: ...Figure 10 6 External Test Setup 1 Figure 10 7 External Test Setup 2 10 10 Service Key Menus ...
Page 185: ...Figure 10 8 External Test Setup 3 Figure 10 9 External Test Setup 4 Service Key Menus 10 11 ...
Page 226: ...Figure 11 3 Power Supply Functional Group Simpli ed Block Diagram 11 6 Theory of Operation ...
Page 231: ...Figure 11 5 Digital Control Group Simpli ed Block Diagram Theory of Operation 11 11 ...
Page 235: ...Figure 11 6 Source Simpli ed Block Diagram Theory of Operation 11 15 ...
Page 244: ...Figure 11 7 Receiver Simpli ed Block Diagram 11 24 Theory of Operation ...
Page 249: ...Figure IDC5S11001 here Figure 11 8 4396B Source Group Block Diagram Theory of Operation 11 29 ...
Page 254: ...Figure 12 1 Top View Major Assemblies 12 4 Replaceable Parts ...
Page 290: ...Figure 12 36 Main Frame Assembly Parts 17 19 12 40 Replaceable Parts ...
Page 294: ......
Page 308: ......
Page 311: ...Figure C 1 Power Cable Supplied Power Requirement C 3 ...
Page 312: ......
Page 324: ......