Agilent Technologies All Catalog Download

Page: 159 / 223

206

English URL

www.agilent.com/find/products

N4903A

J-BERT High-Performance Serial BERT N4903A 12.5 Gb/s and 7 Gb/s

Serial Bit Error Ratio Tester

The Smartest Way to Accurate Jitter Tolerance Test and
Characterization

The J-BERT N4903A High-Performance Serial BERT provides the
only complete jitter tolerance test solution for characterization of
serial gigabit devices.

It offers complete, integrated and calibrated jitter composition

for stressed eye testing of receivers up to 12.5 Gb/s. Automated and
compliant jitter tolerance testing allows quick and accurate charac-
terization for all popular serial bus standards, such as PCI Express,
SATA, FB-DIMM, Display Port, Fibre Channel, CEI, 10 Gigabit
Ethernet and XFP/XFI.

The J-BERT matches the latest serial bus interfaces perfectly

with its ability to analyze undeterministic traffic with idles from the
DUT with the analyzer’s Bit Recovery Mode. The pattern generator
allows setting up complex pattern sequences to bring a device into
loop back mode. To match LVDS and other low voltage standards, all
clock, data inputs and outputs are differential and can handle small
amplitude swings.

Clockless interfaces can be analyzed with the built-in CDR with

tunable loop bandwidth (option CTR). The J-BERT offers differen-
tial subrate clock outputs with any ratio of clock and data signals
without extra equipment. Data and clock outputs support spread
Spectrum Clocking (SSC), commonly used in computer bus
standards.

The J-BERT is an expandable, future-proof BERT platform

where all options can be configured to the current test needs and
upgraded later when those needs change.

It is the ideal choice for R&D and validation teams who charac-

terize and stress chips and transceiver modules with serial I/O ports
up to 12.5 Gb/s.

Specifications

Pattern Generator

Operation Range

Internal clock: 620 Mb/s to 12.5 Gb/s (option C13 and G13) or
7 Gb/s (option C07 and G07)
External clock: 150 Mb/s to 12.5 Gb/s (option C13 and G13) or
7 Gb/s (option C07 and G07)

Data Output

1, differential or single-ended

Output Amplitude

0.1 Vpp – 1.8 Vpp

Jitter

<9 ps pp

Transition Time

<25 ps (10% to 90% and ECL levels)

Crossing Point Adjustable

20% – 80%

Pattern

PRBS 2

–1, n = 7, 10, 11, 15, 23, 31

User-definable memory: 32 Mbit and pattern sequencing

Delay Control Input

200 ps @ 1 GHz

Jitter Tolerance Test

Jitter Sources, Built-in & Calibrated

(option J10)

Random Jitter:

0 to 14 ps rms, up to 1 GHz

Periodic Jitter:

sinewave, rectangular modulation up to 20 MHz,

sinusoidal modulation up to 300 MHz

Sinusoidal Jitter:

multiple UIs up to 5 MHz

Bounded Uncorrelated Jitter:

up to 200 ps pp; according CEI

SSC Clocking

(option J11)

triangular modulation – 0.5% @ 28 to 34 kHz on data and clock outputs

Interference Channel

(option J20)

ISI:

Intersymbol interference by switchable board traces

Sinusoidal Interference

: vertical eye closure, common and differential

mode

Error Detector:

Operation Range

Internal clock: 500 Mb/s to 12.5 Gb/ s (option C13) or 7 Gb/s (option C07)
External clock: 150 Mb/s to 12.5 Gb s (option C13) or 7 Gb/s (option C07)

Data Input

1, differential or single-ended

Delay Adjust

±0.75 ns

Clock Data Recovery

Fixed loop bandwidth: data rate/1667
Variable loop bandwidth (option CTR): 100 kHz to 12 MHz

Sensitivity

<50 mV

Measurement Suite

BER, accumulated, intervals
BERT Scan, “bathtub” curve includes RJ, DJ, TJ
Output Level
Eye Diagram with BER contour and eye masks
Fast Eye Mask
Spectral Jitter
Error Location Capture
Fast Total Jitter Measurement

• Operating range 150 Mb/s to 7 Gb/s or to 12.5 Gb/s provides

enough margin for today’s and tomorrow’s serial interfaces

• Built-in, compliant and calibrated jitter injection with >0.5 UI

(option J10). All in one box: PJ, SJ, RJ, BUJ for stressed eye
testing of a receiver

• Interference channel plug-in with ISI and sinusoidal interference

for emulating channel and noise effects (option J20)

• Automated jitter tolerance test saves programming time

(option J10)

• Transition times <20 ps and jitter <9 ps pp for accurate

measurements

• Built-in Clock Data Recovery (CDR). Tunable loop bandwidth and

compliant CDR settings (option CTR)

• Differential pattern and clock generation and differential analysis
• Sub-rate clock outputs with any ratio 1:n
• Bit recovery mode to analyze undeterministic traffic (option A01)
• External Delay Control Input for injection of external jitter
• SSC clocking (option J11)
• Fast Total Jitter and measurement suite
• Remote programmable via GPIB, LAN, and USB interfaces.

Compatible with existing command set Agilent 71612, 81630
series, N4900 series

• Bench use with intuitive touch-screen user interface based on

Windows XP

• Applications: PCI Express

, SATA, Fully-buffered DIMM, Display

Port, Fibre Channel, CEI, 10 Gb Ethernet, XFP/XFI