Service Guide E8364-90026
5-23
PNA Series Microwave Network Analyzers
Theory of Operation
E8362B, E8363B, E8364B
Receiver Group Operation
A6 SPAM Board (Analog Description)
The A6 SPAM board contains digital and analog circuitry. For digital descriptions, refer to
“A6 SPAM Board (Digital Description)” on page 5-32
In this assembly, the 2nd IF signals from the A, B, R1, and R2 second converters go
through a gain stage where signals less than
−
40 dBm are amplified by 34 dB to ensure
that they can be detected by the analog-to-digital converter (ADC).
All four signals are sampled simultaneously by the ADCs, where they are converted to
digital form. The ADC conversions are triggered by timing signals from the digital signal
processor (DSP) in response to commands from the central processing unit (CPU). The
digitized data is processed into magnitude and phase data by the DSP and sent to the CPU
random access memory (RAM) by way of the peripheral component interconnect (PCI) bus.
The processed and formatted data is finally routed to the display, and to the
general-purpose interface bus (GPIB) for remote operation. Refer to
and Digital Control Group Operation” on page 5-29
for more information on signal
processing.
A35 Receiver Motherboard
The A35 receiver motherboard:
• supplies power and signal leveling control to the A31, A32, A33, and A34 receiver
modules
• selects a phase lock signal and routes it to the A11 phase lock board
• receives the 2nd LO signal from the A10 frequency reference board
Power and Signal Leveling Control
Power and signal leveling control signals are received from the A16 test set motherboard
and routed to each of the receiver modules.
Phase Lock Control
A portion of the 8.333 MHz 1st IF signal from each of the receiver modules is routed to a
multiplexing circuit. For Option 080 (frequency offset mode), an additional signal is input
to the multiplexer from the
A13 Frequency Offset Receiver Assembly (Option 080)
. With
control from the A15 CPU board, one of these five signals is selected for routing to the A11
phase lock board to complete the phase lock loop.
2nd LO Control
The 33.1667 MHz signal from the A10 frequency reference board is divided by four, and
then divided into two paths, designated 2nd LO (a) and 2nd LO (b). The 2nd LO (b) signal
is phase shifted
+
90
°
relative to the 2nd LO (a) signal.
Summary of Contents for E8362B
Page 11: ...Service Guide E8364 90026 1 1 1 Safety and Regulatory Information ...
Page 19: ...Service Guide E8364 90026 2 1 2 General Product Information ...
Page 33: ...Service Guide E8364 90026 3 1 3 Tests and Adjustments ...
Page 83: ...Service Guide E8364 90026 4 1 4 Troubleshooting ...
Page 151: ...Service Guide E8364 90026 5 1 5 Theory of Operation ...
Page 185: ...Service Guide E8364 90026 6 1 6 Replaceable Parts ...
Page 269: ...Service Guide E8364 90026 7 1 7 Repair and Replacement Procedures ...
Page 351: ...Service Guide E8364 90026 8 1 8 General Purpose Maintenance Procedures ...
