5-6
Service Guide E8364-90038
Theory of Operation
PNA Series Microwave Network Analyzers
Source Group Operation
E8362C, E8363C, E8364C
Source Group Operation
The source group produces a stable output signal by phase locking a yttrium-iron-garnet (YIG) oscillator to a
synthesized voltage-controlled oscillator (VCO). Refer to
Table 5-2 on page 5-8
for the full frequency range of
the source. The outputs at the front panel test ports are swept, stepped or CW signals. Maximum leveled
output powers are listed in
Table 5-1 on page 5-4
. For a simple block diagram of the source group, refer to
Figure 5-2
.
The following are described in this section:
•
Band Modes
•
A8 Fractional-N Synthesizer Board
•
A17 L.O. Multiplier/Amplifier 10 (LOMA 10)
•
A18 Multiplier/Amplifier 20 (MA 20)
•
A19 Splitter
•
A20 L.O. Distribution Assembly (LODA)
•
A10 Frequency Reference Board
(including rear-panel interconnects)
•
A11 Phase Lock Board
•
A12 Source 20
•
A21 Source Multiplier/Amplifier 50 (SOMA 50) (E8363C and E8364C Only)
•
A16 Test Set Motherboard
(including rear-panel interconnects)
Band Modes
Table 5-2 on page 5-8
lists the L.O. harmonic number, the synthesizer frequency, the source frequency, and
the frequencies at various other locations within the analyzer for each band. This table is referred to
throughout this chapter and also appears on the overall block diagram at the end of
Chapter 4,
“Troubleshooting.”
The A10 frequency reference board produces a constant phase locked reference signal of 8.333 MHz (1.0416
MHz for Band 0) which is sent to the A11 phase lock board.
The A8 fractional-N synthesizer board produces an LO signal which is sent through the A17–A20 LO
distribution path to the A27–A30 first converters. The frequency is synthesized such that the mixing product
of this LO signal with the main source output is a constant 8.333 MHz. In the A31–A34 receiver modules,
this 1st IF signal is mixed with the 2nd LO signals to produce a constant 2nd IF signal at 41.667 kHz.
A portion of the 1st IF signal is passed through the phase lock multiplexer on the A16 test set motherboard
back to the A11 phase lock board to complete the phase lock loop. For Option 080 (frequency offset mode),
this phase lock signal comes from the A13 frequency offset receiver. Refer to
“Frequency Offset Group
Operation (Options 080 and 081)” on page 5-24
.
The A10 frequency reference board also produces a constant 33.1667 MHz signal which is passed to the A35
receiver motherboard where the frequency is divided by four to produce a constant 2nd LO signal of 8.29167
MHz. It is then divided into two signals, the 2nd LO (a) and the 2nd LO (b). The 2nd LO (b) signal is phase
shifted
90
relative to 2nd LO (a). Both of these signals are then distributed to each of the four receiver
modules.
Summary of Contents for E8362C
Page 11: ...Service Guide E8364 90038 1 1 1 Safety and Regulatory Information ...
Page 21: ...Service Guide E8364 90038 2 1 2 General Product Information ...
Page 33: ...Service Guide E8364 90038 3 1 3 Tests and Adjustments ...
Page 81: ...Service Guide E8364 90038 4 1 4 Troubleshooting ...
Page 137: ...Service Guide E8364 90038 5 1 5 Theory of Operation ...
Page 171: ...Service Guide E8364 90038 6 1 6 Replaceable Parts ...
Page 257: ...Service Guide E8364 90038 7 1 7 Repair and Replacement Procedures ...
Page 341: ...Service Guide E8364 90038 8 1 8 General Purpose Maintenance Procedures ...
