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The Execution Error Register is read and cleared using the ‘EER?’ command. On power up this
register is set to 0 for all interface instances.
There is no corresponding mask register: if any of these errors occurs, then bit 4 of the
Standard Event Status Register will be set. This bit can be masked from any further
consequences by clearing bit 4 of the Standard Event Status Enable Register.
Status Byte Register (STB) and GPIB Service Request Enable Register (SRE)
These two registers are implemented as required by the IEEE Std. 488.2.
Any bits set in the Status Byte Register which correspond to bits set in the Service Request
Enable Register will cause the RQS/MSS bit to be set in the Status Byte Register, thus
generating a Service Request on the bus.
The Status Byte Register is read either by the *STB? query, which will return MSS in bit 6, or by
a Serial Poll which will return RQS in bit 6. The Service Request Enable register is set by the
*SRE <
NRF
> command and read by the *SRE? Query.
Bits 7 & 3 :
Not used, permanently 0.
Bit 6
MSS/RQS
. This bit (as defined by IEEE Std. 488.2) contains alternatively the
Master Status Summary message returned in response to the *STB? query, or the
Requesting Service message returned in response to a Serial Poll.
The RQS message is cleared when polled, but the MSS bit remains set for as long
as the condition is true.
Bit 5
ESB.
The
Event Status
Bit. This bit is set if any bits set in the Standard Event Status
Register correspond to bits set in the Standard Event Status Enable Register.
Bit 4
MAV.
The
Message Available
Bit. This will be set when the instrument has a
response message formatted and ready to send to the controller.
The bit will be cleared after the Response Message Terminator has been sent.
Bit 2
LIM3
. The
Output3 Limit Status
Bit. This will be set if any bits in the Limit Event
Status register for output3 are set and corresponding bits are set in the Limit
Event Status Enable register LSE3.
Bit 1
LIM2
. The
Output2 Limit Status
Bit. This will be set if any bits in the Limit Event
Status register for output2 are set and corresponding bits are set in the Limit
Event Status Enable register LSE2.
Bit 0
LIM1
. The
Output1 Limit Status
Bit. This will be set if any bits in the Limit Event
Status register for output1 are set and corresponding bits are set in the Limit
Event Status Enable register LSE1.
GPIB Parallel Poll (PRE)
Complete Parallel Poll capabilities are offered by this instrument as defined in IEEE Std. 488.1.
The Parallel Poll Enable Register (which is set by the *PRE <
NRF
> command and read by the
*PRE? query) specifies which bits in the Status Byte Register are to be used to form the
ist
local message. If any bit is ‘1’ in both the STB and the PRE then
ist
is ‘1’, otherwise it is ‘0’. The
state of the
ist
message can also be read directly by the *IST? query.
The physical layer protocol of the Parallel Poll (determining which data line is to be driven and
its logic sense) is configured by the PPC and PPE commands and released by the PPU and
PPD commands in the manner defined by the standard. The instrument implements passive
pull-up on the DIO lines during Parallel Poll.
Query Error Register - GPIB IEEE Std. 488.2 Error Handling
These errors are much more likely to occur on the semi-duplex GPIB interface, which requires
the instrument to hold a response until addressed to talk by the controller. All the other
interfaces provide full duplex communication, with buffering in the physical layer which will
