II. CHIPSET FEATURES SETUP
25 MHz
33 MHz
40 MHz
50 MHz
AT Bus Clock
CLK/3 or
CLK/6
CLK/2 or
CLK/4
CLK/2.5 or
CLK/5
CLK/3 or
CLK/6
SRAM Read
Burst
3111
3222
3222
3222
SRAM Write WS
0WS
0WS
1WS
1WS
Special SRAM
Wait State (WS)
Disabled
Enabled
Disabled
Disabled
DRAM Write WS
0WS
1WS
1WS
1WS
DRAM Read WS
2WS
3WS
3WS
3WS
RAS Precharge
2 Sysclk
3 Sysclk
3 Sysclk
3 Sysclk
RAS to CAS
Delay
1 Sysclk
1 Sysclk
2 Sysclk
2 Sysclk
F0000 Cacheable
:
Enabled
C0000 Cacheable
:
Enabled
Cacheable Range
:
0-128M
DRAM Page Mode
:
Slow Page Mode
15-16MB Access
:
Normal
1MB Cache Memory
:
Disabled
VGA Type
:
Standard
PCI Arbitration Rotate Priority
:
Disabled
PCI Post-Write Fast
:
Disabled
CPU Master Post-Write Buffer
:
4
CPU Master Post-Write Burst Mode
:
Disabled
CPU Master Fast Interface
:
Disabled
PCI Master Post-Write Buffer
:
4
PCI Master Post-Write Burst Mode
:
Disabled
PCI Master Fast Interface
:
Disabled
CPU Master DEVSEL# Time-Out
:
6 PCICLK
PCI Master DEVSEL# Time-Out
:
4 PCICLK
486VP System Board User's Manual Page 3
Summary of Contents for 486VP
Page 1: ...486VP VL PCI System Board USER S MANUAL Revision 1 0...
Page 9: ...3 6V 60mA on board battery Page 8 486VP System Board User s Manual...
Page 11: ...Page 10 486VP System Board User s Manual...
Page 12: ...FIGURE 486VP System Board User s Manual Page 11...
Page 29: ...PG UP PG DN Modify the Setup Item Page 28 486VP System Board User s Manual...