Pin No.
Pin Name
I/O
Description
36
82
83
84
85
86
87
88
89
90
91
92, 93
94
95
96
97
98 ~ 100
R/C
G4
G3
G2
G1
COMPOSITE
SYNC. (INV)
—
POWER FAIL
IIC CLOCK
IIC DATA
S9, S8
S7/FLD ENABLE
S6/FLD CLOCK
S5/FLD DATA IN
S4/FLD DATA OUT
S3 ~ S1
I
O
I
—
I
O
O
O
O
O
I
O
O
1. This pin receives remocon data through RC5F1, which amplifies and detects the
R/C signal.
2. After input signal is decoded in µ-COM (IC501), and performs related key
operation.
For LED clock model.
1. Input C-Sync (composite sync) to confirm whether video signal is present or not.
2. Confirms by counting 1H (63.5µsec) horizontal sync for a fixed time period.
Not connected.
1. When a power failure is detected, this pin goes “L” and the following sequence of
events occurs.
2. Power failure detector timing sequence.
A reference CLOCK for Hi-Fi, TU/IF, MTS, SPEAKER
A reference DATA for Hi-Fi, TU/IF, MTS, SPEAKER
For LED clock model.
Outputs chip enable signal for FLD Drive IC (IC5F1).
Outputs clock signal to operate FLD Drive IC (IC5F1).
Serial interface signals for FLD Drive IC control.
For LED clock model.
AC POWER ON
AC POWER OFF
t
t
t
t
t
t
Power failure
compensation cancel state
Power failure
compensation
state
(
µ
-COM memory loss state)
Vcc for (Back-up)
AVcc No (Back-up)
Power failure signal
10MHz OSC
36.768kHz OSC
Reset pulse
Power failure
compensation relation
Normal
operation
state
5.3VA
