-36-
1
2
3
4
5
6
7-9
10-15
16
17
18
19
20
21
22
23-29
30-36
37
38
39
40
41
42
43
44-46
47
48
49
50-52
53
54
55
56-58
59
60
61
62-64
65
66
67
68
IC, CL680
Pin No.
Pin Name
I/O
Description
NC
VSS
CD BCK
CD DATA
CD LRCK
CD C2PO
NC
MD0-MD5
VSS
MD6
VDD3
MD7
VSS
MD8
VDD3
MD9-MD15
NC
________
MCE
__________
MWE
VSS
________
CAS
VDD3
___________
RASO
___________
RASI
MA10-MA8
VSS
MA7
VDD3
MA6-MA4
VSS
MA3
VDD3
MA2-MA0
PGIO7
______________
RESET
VDD MAX IN
NC
AGND DAC
A DAC
COMPOS OUT
AGND DAC
—
—
I
I
I
I
—
I/O
—
I/O
—
I/O
—
I/O
—
I/O
—
—
O
—
O
—
O
O
O
—
O
—
O
—
O
—
O
I/O
I
—
—
—
—
O
—
No connection.
GND.
Bit clock input from CD DSP.
Data input from CD DSP.
LRCK input from CD DSP.
C2 pointer input from CD DSP.
No connection.
DRAM/ROM interface. (DATA)
Ground.
DRAM/ROM interface. (DATA)
Power supply 3.3V.
DRAM/ROM interface. (DATA)
Ground.
DRAM/ROM interface. (DATA)
Power supply 3.3V.
DRAM/ROM interface. (DATA)
No connection.
ROM chip enable.
DRAM write enable.
Ground.
DRAM/ROM interface.
Power supply 3.3V.
DRAM/ROM interface.
DRAM/ROM interface. (Address)
Ground.
DRAM/ROM interface. (Address)
Power supply 3.3V.
DRAM/ROM interface. (Address)
Ground.
DRAM/ROM interface. (Address)
Power supply 3.3V.
DRAM/ROM interface. (Address)
Programmable I/O.
Reset input.
Power supply - VDDMAX. (5.0V)
No connection.
Analog ground.
Analog power supply (DAC) : 3.3V.
Composite out.
Analog ground.
Summary of Contents for LCX-K117
Page 12: ... 12 SCHEMATIC DIAGRAM 1 MAIN 2B 1 2 DECK 2B Q243 244 ...
Page 13: ... 13 SCHEMATIC DIAGRAM 2 MAIN 2B 2 2 2B ...
Page 16: ... 16 SCHEMATIC DIAGRAM 3 VCD 1 2 2B ...
Page 17: ... 17 SCHEMATIC DIAGRAM 4 VCD 2 2 DAC_CK V ID ...
Page 18: ... 18 SCHEMATIC DIAGRAM 5 FR LED 2B D ...
Page 20: ... 20 SCHEMATIC DIAGRAM 6 PT PTX901 ...
Page 24: ... 24 FL AIWA4239ACL 13 GRID ASSIGNMENT ANODE CONNECTION GRID ASSIGNMENT ANODE CONNECTION ...
Page 25: ... 25 VOLTAGE CHART ...
Page 26: ... 26 ...
Page 27: ... 27 ...
Page 28: ... 28 ...