Aiwa LCX-K277, Service Manual

-34-

GND connection terminal. (Digital ground terminal)

External X’tal and capacitor for internal sync generator, or the external clock are

connected to this terminal. (2fsc or 4fsc)

Either the external clock input mode or the X’tal generator mode is selected by this selector

terminal. L: X’tal generator mode, H: External clock input.

Blank signal (character and the green ORed signal) is output from this terminal. (MODE 0:

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composite sync signal is output at H) When reset (RST terminal = L), the X’tal clock signal is

output. (It is not output when reset by the reset command)

External coil and capacitor for the character output dot clock generator are connected

to this terminal.

The character signal is output from this terminal. (MOD 0: when H, the external sync signal

identification signal is output from this terminal. This output signal tells whether the external

________

sync signal is present or not. When external sync signal is present, H is output) When reset (RST

terminal = L), the dot clock signal (LC oscillator) is output. (It is not output when reset by the

reset command)

Enable signal for the serial data input is input to this terminal. The serial data input is enabled at

L. Pull-up resistor is built-in. (Hysteresis input)

Clock of the serial data input is input to this terminal. Pull-up resistor is built-in. (Hysteresis

input)

Serial data input terminal. Pull-up resistor is built-in. (Hysteresis input)

Power supply for the composite video signal level adjustment. (Analog power supply)

Composite video signal output terminal.

Connected to GND or not connected.

Composite video signal input terminal.

Power supply. (+5V digital power supply)

Video signal for the internal sync separator circuit is input to this terminal. (When the internal

sync separator circuit is not used, the horizontal sync signal or composite sync signal is input to

this terminal)

Internal sync separator circuit bias voltage monitoring terminal.

The composite sync output signal of the internal sync separator circuit is output from this

terminal. (H: MOD 1. H: during internal sync mode. L: during external sync mode) (When

internal sync separator circuit is not used, the SYN IN input signal is output from this terminal)

The output signal of the SEP OUT terminal is integrated so that the vertical sync signal is input

to this terminal. An integrator circuit must be connected between the SEP OUT terminal and this

terminal. When this terminal is not used, it must be connected to VDD1.

When selecting any of the NTSC or PAL or PAL-M or PAL-N system, the pin setting has

priority. When L, the NTSC system is selected after resetting. Selection of either NTSC or PAL

or PAL-M or PAL-N system by the command becomes effective. H: PAL-M system.

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Controls whether or not to input the VSYNC signal to the SEPIN input. L: to input the VSYNC

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signal. H: not to input the VSYNC signal.

System reset input terminal. Pull-up resistor is built-in. (Hysteresis input)

VSS1

Xtal IN

Xtal OUT

CTRL1

BLANK

OSC IN

OSC OUT

CHARA

______

CS

SCLK

SIN

VDD2

CV OUT

NC

CV IN

VDD1

SYN IN

SEP C

SEP OUT

SEP IN

CTRL2

CTRL3

________

RST

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

IC DESCRIPTION-5/7 (LC74781M)-1/2

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Pin No.

Pin Name

I/O

Description