Pin Descriptions
Pinout Information
2.2.4
Miscellaneous Pins
Table 2-4
provides detailed descriptions for Miscellaneous Pins.
2.2.5
Host Interface Pins
Table 2-5
provides detailed pin descriptions for the Host Interface.
2.2.6
Memory Pins
Table 2-6
provides detailed pin descriptions for Memory.
Table 2-4 Miscellaneous Pin Descriptions
Name
Pin(s)
Type
Function
XTALI
40
I
Crystal oscillator input. Connect to an external 10MHz crystal.
XTALO
41
O
Crystal oscillator output. Connect to an external 10MHz crystal.
RESETn
55
I
Hardware asynchronous reset. The signal is active low. Must be continuously asserted
for a minimum of 100 µs after power-up to satisfy the SDRAM power-up requirement.
[Input, Schmitt trigger, pull-up, 5V-tolerant]
CGMS
146
I
CGMS Enable
TCK
50
I
Debug port test data clock. TCK provides the clock input for the Test Bus (also known
as the Test Access Port).
TDI
51
I
Debug port test data in. TDI transfers serial test data into VISTA. TDI provides the
serial input necessary for JTAG specification support.
TDO
48
O
Debug port test data out. TDO transfers serial test data out of VISTA. TDO provides
the serial input necessary for JTAG specification support.
TMS
52
I
Debug port test mode select. TMS is a JTAG specification support signal used by
debug tools.
TRSTn
53
I
Debug port test reset. TRSTn resets the Test Access Port (TAP) logic. TRSTn must be
driven low during power on RESETn.
TEST
56
I
Test mode. Active high. Must be low during normal operation. [Input, pull-down, 5V-
tolerant]
TESTCLK
144
I
Used for testing, can be used to supply display clock. [Input, pull-down, 5V-tolerant]
NC 201
-
No connect.
NC
62, 63,
194,195
-
No connect.
Table 2-5 Host Interface Pin Descriptions
Name
Pin(s)
Type
Function
2WCLK
45
I
Clock signal of two-wire serial bus. [Input, pull-up, 5V-tolerant]
2WDAT
47
I/O
Data signal of two-wire serial bus. [Bi-directional, tri-state 4mA drive output, 5V-
tolerant]
2WA1
43
I
Programmable two-wire serial bus address bit 1. [Input, pull-down, 5V-tolerant]
2WA2
44
I
Programmable two-wire serial bus address bit 2. [Input, pull-down, 5V-tolerant]
Table 2-6 Memory Pin Descriptions
Name
Pin(s)
Type
Function
MCLK
229
O
SDRAM clock. This signal is rising edge active. [Tri-state output, 8mA drive,
5V-tolerant]
MCLKFB
223
I
SDRAM clock feedback. For latching in read data. [Input, 5V-tolerant]
Summary of Contents for LCT2662
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Page 111: ...Exploded View Diagram Exploded View Diagram ...