T
vd
T
vb
T
v
T
h
6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
The input signal timing specifications are shown as the following table and timing diagram
.
Signal Item
Symbol
Min.
Typ.
Max. Unit
Note
Frequency
1/Tc
60
86
88 MH
Z
LVDS Receiver Clock
Input cycle to
cycle jitter
Trcl - - 200
ps
Setup Time
Tlvsu
600
-
-
ps
LVDS Receiver Data
Hold Time
Tlvhd
600
-
-
ps
Fr
5
47
50
53 Hz
Frame Rate
Fr
6
57
60
63 Hz
(2)
Total Tv
778
795
888
Th
Tv=Tvd+Tvb
Display Tvd
768
768
768
Th -
Vertical Active Display Term
Blank Tvb
10
27
120
Th
-
Total Th
1436
1798
1936
Tc
Th=Thd+Thb
Display Thd
1366
1366
1366
Tc -
Horizontal Active Display Term
Blank Thb
70
432
570
Tc
-
Note (1) Since this module is operated in DE only mode, Hsync and Vsync input signals should be set to
low logic level. Otherwise, this module would operate abnormally.
(2) Please refer to 5.1 for detail information.
INPUT SIGNAL TIMING DIAGRAM
DE
T
hb
Valid display data (1366
clocks)
T
c
DCLK
T
hd
DE
DATA
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Summary of Contents for LCT3285TAJ
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