10
Standard Definition Video Control Port
D16
SVCLK
SV pels clock input
C14
SVHSYNC
SV horizontal synchronization signal input
B14
SVVSYNC
SV vertical synchronization signal input
A14
SVODD
Scan status input
A17
SVDV
SV data input
Standard Definition Video Data Port
D14,D15,A15,A16,
B15,B16,C15,C16
SVDATA7~
SVDATA0
SV ITU656 data input
Video Control Port
A20
VCLK
Video pels clock signal
D19
VHS_CSYNC
Video horizontal synchronization signal input
C20
VVS
Video vertical synchronization signal input
B20
VODD
Scan status input
D20
VDV (VSOG)
Video data input
B17
VCLAMP
Video clamp enable output
A21,A22,A23,B21,
B22,C21,C22,D21
VGRN7~ VGRN0
Green signal or Y signal input
C17,C18,C19,A18
A19,B18,B19,D18
VRED7~ VRED0
Red signal or V/Cr/Pr signal input
B23,B24,B25,A24
A25,C23,C24,D24
VBLU7~ VBLU0
Blue signal or U/Cb/Pb signal input
Screen Control Port
A26
PPWR
Screen power control
B26
PBIAS
Screen bias control
D26
,
C25
,
C26
PWM2 ~PWM0
Pulse width modulation output
AC7
DCLK
Pels clock output
AC16
OEXTR
Connect external LVDS bias resistance
LVDS Port
AE14~AE16,AE19~
AE23,AF13~AF16
AF19~AF23,AF11
A0-~A3-, A0+~A3+
B0-~B3-, B0+~B3+
Low voltage difference data input
AD14,AD11,AE13
AE11,AC11,AF10
LVDS_SHIELD[5] ~
LVDS_SHIELD[0]
Low voltage difference protect output
AE12,AF12,
AF20,AE20
AC+,AC-,BC+,BC- Low
voltage
difference protect input
Screen Port Power Supply
AD12,AD13,AC12 LVDSB_3.3
LVDS B channel power supply
AC13,AC14,AC15
LVDSB_GND
B channel ground
AC20,AC21,AC22 LVDSA_3.3
LVDS A channel power supply
AD19,AC19,AC20
LVDSA_GND
A channel ground
AE17
VDDD33_LVDS
Analog power supply
AD17 VSSD33_LVDS
Analog
ground
Clock Composite and Power Supply
G4
XTAL
crystal oscillator interface