ASAHI KASEI
[AKD4584]
<KM065802>
2009/06
- 10 -
(2) Master Mode
(2-1) A/D evaluation using DIT function of AK4584
(
Default
)
Using X’tal (X1), PORT4 (DIT) and J6 (TX). Nothing should be connected to J7 (RX), PORT1 (DIR), PORT5
(DIR) and PORT6 (ROM). The bi-phase data is output from TX3. JP6 (EXT) should be short. In normal speed,
double speed mode and quad speed mode, JP3 (XTI), JP4 (MCLK), JP5 (BCFS) and JP7 (LRFS) should be open.
JP10
MCLK
JP3
XTI
JP14
LRCK
JP6
EXT
JP11
BICK
EXT
DIR
DI
R
EXT
AD
C
JP15
SDTI
ADC
DIR
EXT
DIR
•
Clock Setting
(2-1-1) Select MCKO1
JP5
BCFS
JP7
LRFS
JP4
MCLK
x1
x4
x4
x2
x1
JP1
MCKO
M2
M1
x2
x1
(2-1-2) Select MCKO2
JP5
BCFS
JP7
LRFS
JP4
MCLK
x1
x4
x4
x2
x1
JP1
MCKO
M2
M1
x2
x1
•
SW2 (MODE) setting (See Table 1)
Normal speed and double speed are same setting.
(1)
When XTALE is “H”, MCLK can output from MCKO1/2 pins though AK4584 is powered down.
(2)
When DMCK is “H”, MCKO1 output is disabled.
H
L
1 2 3 4 5
8
6 7
9 10
DI
F
0
DI
F
1
DI
F
2
O
C
KS0
O
C
KS1
CM
0
TES
T
3
XT
A
L
E
DM
CK
MS