7
card replaces standard video connections
with a variety of analog and digital video
formats
Video Processor
?
Stretch S5610 with 2GB, 400MHz
DDRAM memory, 300MHz Xtensa CPU
core, two reconfigurable Instruction Set
Extension Fabric (ISEF) units
?
Lattice ECP2 FPGA with 6 banks of 64MB
16-bit, 400MHz DDR memory each for the
on-board image-buffering and formatting.
Software Development
?
Microsoft Windows XP .NET Framework
?
Stretch C Integrated Design Environment
(IDE)
?
Alacron ALRT run-time libraries, libJPEG,
libTIFF, and other video compression and
processing libraries
System Requirements
PCI-X compliant system running MS
Windows XP SP2 and higher with at least 1
GB system memory
Temperature
0
o
C (32
o
F) to 55
o
C (131
o
F)
Relative Humidity: up to 95% (non-
condensing)
O
PTIONAL
F
EATURES
?
Video I/O Expansion mezzanine daughter card
?
Unassisted by Host Fast-X operations made possible by local application boot of the
Stretch S5610 processor from 32MB of on-board FLASH.
HARDWARE OVERVIEW
This chapter provides an overview of Fast-X hardware functional units and describes their
operations.
FAST-X
BLOCK
DIAGRAM
The key to the Fast-X video data handling and video processing capabilities is its hybrid
architecture that augments processing power and data handling of Stretch S5610 Software-
Configurable DSP Processor (SCP) with the extended bit-handling by the Lattice ECP FPGA.
The front-end Lattice FPGA provides video data buffering, formatting, and steering. It contains
multiple state machines needed to handle structured video information in the input streams.
The front-end FPGA counts and time-stamps video frames before passing them to the Stretch
processor. Triggering and camera strobes can be generated from the on-board software or
from external inputs to the board. The data-path FPGA is configured by the Stretch processor
from the program file stored in local Flash memory or received from the Host.
