Albalá Ingenieros DVM3001C02, Manual

Albalá Ingenieros | Manual 

DVM3001C02

EDH_ERROR_A_MASK

0x02

0x40

N

N

Allows masking EDH errors (Section A)
0=Disabled, 1=Enabled

EDH_ERROR_B_MASK

0x02

0x80

N

N

Allows masking EDH errors (Section B)
0=Disabled, 1=Enabled

STATUS

Name

add

ext

msk

snmp trap

Description

NO_SIG_A

0x01

0x01

Y

Y

Input signal status (Section A)
0=OK,1=Fail

NO_SIG_B

0x01

0x02

Y

Y

Input signal status (Section B)
0=OK,1=Fail

MAX_EQ_A

0x01

0x04

Y

N

Indicates maximum equalization (Section A)
0=OK,1=Fail

MAX_EQ_B

0x01

0x08

Y

N

Indicates maximum equalization (Section B)
0=OK,1=Fail

UNLOCK_A

0x01

0x10

Y

Y

Indicates signal unlock fail (Section A)
0=OK,1=Fail

UNLOCK_B

0x01

0x20

Y

Y

Indicates signal unlock fail (Section B)
0=OK,1=Fail

EDH_ERROR_A

0x01

0x40

Y

N

EDH status (Section A)
0=OK,1=Fail

EDH_ERROR_B

0x01

0x80

Y

N

EDH status (Section B)
0=OK,1=Fail

EDH_PRES_A

0x02

0x01

Y

N

EDH packet presence (Section A)
0=No, 1=Yes

EDH_PRES_B

0x02

0x02

Y

N

EDH packet presence (Section B)
0=No, 1=Yes

FORMAT_A

0x02

0x04

Y

N

Format (Section A)
0=625, 1=525

FORMAT_B

0x02

0x08

Y

N

Format (Section B)
0=625, 1=525

MUTE_A

0x02

0x10

Y

N

Output muted (Section A)
0=No, 1=Yes

MUTE_B

0x02

0x20

Y

N

Output muted (Section B)
0=No, 1=Yes

FULL_EDH_A

0x03

0x01

N

N

Full field EDH bit status (Section A)
0=OK,1=Fail

FULL_EDA_A

0x03

0x02

N

N

Full field EDA bit status (Section A)
0=OK,1=Fail

FULL_IDH_A

0x03

0x04

N

N

Full field IDH bit status (Section A)
0=OK,1=Fail

FULL_IDA_A

0x03

0x08

N

N

Full field IDA bit status (Section A)
0=OK,1=Fail

FULL_UES_A

0x03

0x10

N

N

Full field UES bit status (Section A)
0=OK,1=Fail

FULL_EDH_B

0x04

0x01

N

N

Full field EDH bit status (Section B)
0=OK,1=Fail

FULL_EDA_B

0x04

0x02

N

N

Full field EDA bit status (Section B)
0=OK,1=Fail

FULL_IDH_B

0x04

0x04

N

N

Full field IDH bit status (Section B)
0=OK,1=Fail

FULL_IDA_B

0x04

0x08

N

N

Full field IDA bit status (Section B)
0=OK,1=Fail

FULL_UES_B

0x04

0x10

N

N

Full field UES bit status (Section B)
0=OK,1=Fail

ACT_EDH_A

0x05

0x01

N

N

Active picture EDH bit status (Section A)
0=OK,1=Fail

ACT_EDA_A

0x05

0x02

N

N

Active picture EDA bit status (Section A)
0=OK,1=Fail

ACT_IDH_A

0x05

0x04

N

N

Active picture IDH bit status (Section A)
0=OK,1=Fail

ACT_IDA_A

0x05

0x08

N

N

Active picture IDA bit status (Section A)
0=OK,1=Fail

ACT_UES_A

0x05

0x10

N

N

Active picture UES bit status (Section A)
0=OK,1=Fail

ACT_EDH_B

0x06

0x01

N

N

Active picture EDH bit status (Section B)
0=OK,1=Fail

ACT_EDA_B

0x06

0x02

N

N

Active picture EDA bit status (Section B)
0=OK,1=Fail

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