HR-16/HR16B Service Manual 1.00
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C62 was added to the analog rails of the op-amp to prevent oscillation during power up, and may
need to be added to some older units (see section 7.20).
3.0 The 8031
The 8031 MPU is the heart of the HR-16's control section. It handles everything from keypad
input and MIDI I/O, to sequencing. Note that the 8031 data buss serves a dual purpose. This buss
multiplexes between low order addresses (1st 8 bits), and data. Latch U7 is used to hold the low
order address half, during 8031 read and write cycles. The EPROM (U11) is used to hold 8031
program information. The SRAM (U12) holds system variables, as well as user sequence data. Z1
provides the 12MHz 8031 clock. MIDI I/O is handled through the 8031's built in RXD (Read Serial
Data), and TXD (Transmit Serial Data) ports. Tape I/O and piezo input is handled through the built
in 8031 I/O ports. DM3AG ASIC control, and LCD output are handled through memory mapped I/O
(see section 3.2). Keypad decoding uses both forms of I/O (see section 3.3).
3.1 Reset
The 8031 reset circuit is perhaps the single most important circuit in the HR-16. When this
circuit is functioning incorrectly, problems ranging from loss of battery backup to a complete lock-up
of the machine can occur. A thorough knowledge of the operation of this circuit will greatly facilitate
troubleshooting this unit.
This circuit uses the differential between raw +10V and reg5V to generate the
required signals for system RESET. This is necessary due to fact that the system MUST be in a
reset state while powering down, otherwise random noise on the 8031 data and address busses
could corrupt SRAM data, and destroy any hope that the battery backup will work. R28, R29, and
the 5.1V zener diode (D15) work together as a voltage divider to the base of Q4, and is designed so
that transistor Q4 will turn on when the raw +10V supply is roughly 7V. This is to ensure that
RESET does not occur until after the +5V regulator is fully functioning (i.e. +5V rail is solid). If
RESET occurs too early, noise on the +5V rail can cause data corruption. Before the Q4 turn on
threshold, Q5 remains turned on (the base of the transistor being pulled up by R30). This in turn
holds the voltage across C20 at .3 volts. This is below the threshold (set by R25 and R96)
necessary to turn on the comparator U1 (pins 10, 11 and 13), leaving the reset line high (pulled up
by R10). Once the raw supply has reached a sufficient level to turn on Q4 (roughly 7V), Q4 will pull
the base of Q5 low, turning it off. This allows C20 to begin charging through R24. Once C20 has
charged to roughly 2.5V, the comparator will switch states and hold it low (due to the hysteresis
established by R27). This completes the reset cycle during power up.
During power down, the opposite occurs, ensuring that the 8031 is held in a reset state
during power down as well. This is necessary in order to prevent random data from being written
into the SRAM during shutdown. Be aware that this can cause unusual unit lockups to occur if the
circumstances are just right. For example, if an HR-16 was shut off while in record mode, it's
possible the 8031 was put into reset in the middle of writing a two byte pointer into memory. If only
one of those bytes is written before reset, then it may point to an incorrect location in memory
(battery backup holds the incorrect data). When the unit is powered back up, the incorrect pointer
may send the software into "never never land" where the only way to recover is to reinitialize the
unit.
