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Rockwell Automation Publication 1718-UM001A-EN-E - December 2019
Appendix C
Additional HART Protocol Information
Message Structure
Read this section for a description of transaction procedure, character coding,
and message structure of the HART protocol. These correspond to layer 2 (data-
link layer) of the OSI protocol reference model.
Master-slave Operation
HART is a master-slave protocol. This means that each message transaction is
originated by the master; the slave (field) device replies when it receives a
command message addressed to it. The reply from the slave device acknowledges
that the command was received and can contain data requested by the master.
Multiple Master Operation
The HART protocol provides for two active masters in a system: one primary
and one secondary. The two masters have different addresses. Each can positively
identify replies to its own command messages. The 1719-IF4HB or 1719-CF4H
module acts as primary master. A secondary master, such as a handheld
configuration device, may also be connected.
Transaction Procedure
HART is a half-duplex protocol. After completion of each message, the FSK
carrier signal must be switched off to let the other station transmit. The carrier
control timing rules state that the carrier should be turned on not more than 5 bit
times before the start of the message (that is, the preamble) and turned off not
more than 5 bit times after the end of the last byte of the message (the checksum).
The master is responsible for controlling message transactions. If there is no reply
to a command within the expected time, the master should retry the message.
After a few retries, the master should abort the transaction, because presumably
the slave device or the communication link has failed.
After each transaction is completed, the master should pause for a short time
before sending another command, to provide an opportunity for the other master
to break in if it wishes. This way, two masters (if they are present) take turns at
communicating with the slave devices. Typical message lengths and delays allow
two transactions per second.
Burst Mode
Burst mode is not supported by the 1719 HART analog modules.