ADM-PCIE-8K5-FH User Manual
3.4 DDR4 SDRAM
Two banks of DDR4 SDRAM memory are soldered down to the board. While the factory default is 8GB/per bank,
16GB/bank is also supported through a build variant. Please see
Order Code
for all order options. The memory
interface is 72-bit wide data (64 data + 8 ECC). Maximum signaling rate is 2400 MT/s for 16GB total and
1688MT/s with 32GB total.
Memory solutions are available from the Xilinx Memory Interface Generator (MIG) and must use Vivado 2016.1
or later. An example project with traffic generator is available with purchase of the ADM-PCIE-8K5 SDK.
However, all the information required to generate a complete MIG IP core is available within this user guide.
3.4.1 MIG IP setup requirements rev2 + newer PCBs
8GB per bank, rev2 and newer PCB
•
Vivado 2016.3 IP Catalog: DDR4 SDRAM (MIG)
•
Memory Device Interface Speed (ps): 937
•
Reference Input Clock speed (ps): 3332
•
Custom Parts Data File: Checked, use 'adm-pcie-'8k5_custom_parts_2400.csv' downloaded from
www.alpha-data.com/8k5
•
Configuration: Components
•
Memory Part: CUSTOM_DBI_MT40A1G8PM-083E
•
Data Mask and DBI: NO DM DBI WR RD
•
IO locations found in appendix
Page 10
Functional Description
ad-ug-1342_v1_0.pdf
