ADM-SDEV-BASE/XCKU060 User Manual
V1.0 - 27th November 2018
3.3.1 Reference Clocks (REFCLK400M and FABRIC_CLK)
The fixed reference clocks REFCLK400M and FABRIC_CLK are differential HSTL signals.
REFCLK400M is used as the input clock for the DDR SDRAM interface.
FABRIC_CLK is used as the reference clock for the IO delay control block (IDELAYCTRL).
Signal
Frequency
Target FPGA Input
IO Standard
"P" pin
"N" pin
REFCLK400M
400 MHz
IO BANK 67
HSTL
H18
H17
FABRIC_CLK
200 MHz
IO BANK 67
HSTL
H19
G19
Table 4 : DDR REFCLK Connections
3.3.2 Programmable Clocks (PROGCLK0 and PROGCLK1)
There are two programable clock sources that are forwarded throughout the FPGA. These clocks are
programmable through the Alpha Data ADA-SDEV-BASE SDK. PROGCLK0 and PROGCLK1 are generated by a
dedicated programmable clock generator IC and offer extremely high frequency resolutions (1ppm increments).
Signal
Frequency
Target FPGA Input
IO Standard
"P" pin
"N" pin
PROGCLK0[0]
5 - 400 MHz
IO BANK 45
LVDS
AL27
AL28
PROGCLK0[1]
5 - 400 MHz
MGTREFCLK1_224
LVDS
AP10
AP9
PROGCLK0[2]
5 - 400 MHz
MGTREFCLK1_127
LVDS
V32
V33
PROGCLK0[3]
5 - 400 MHz
IO BANK25
LVDS
AN36
AN37
Table 5 : PROGCLK0 Connections
Note: PROGCLK0[3:0] are all buffered copies of the same clock signal. The default (factory set) frequency of
PROGCLK0 = 400MHz.
Signal
Frequency
Target FPGA Input
IO Standard
"P" pin
"N" pin
PROGCLK1[0]
5 - 400 MHz
MGTREFCLK1_225
LVDS
AK10
AK9
PROGCLK1[1]
5 - 400 MHz
IO BANK 64
LVDS
AP19
AP18
PROGCLK1[2]
5 - 400 MHz
IO BANK 48
LVDS
J26
H26
PROGCLK1[3]
5 - 400 MHz
MGTREFCLK1_226
LVDS
AC8
AC7
Table 6 : PROGCLK1 Connections
Note: PROGCLK1[3:0] are all buffered copies of the same clock signal. The default (factory set) frequency of
PROGCLK1 = 150MHz.
3.3.3 Module to Carrier Global Clocks (CLK_M2C)
Each connected FMC board can generate a number of differential Global clocks (as per the FMC standard).
They each connect to an global clock input on the FPGA.
Page 9
Functional Description
ad-ug-1360_v1_0.pdf
