ADM-VPX3-9V2 User Manual
2.2 Chassis Requirements
2.2.1 PCI Express
The ADM-VPX3-9V2 is capable of PCIe Gen 3 with up to 16 lanes, using the Xilinx Integrated Block for PCI
Express.
2.2.2 Mechanical Requirements
A 3U VPX compliant backplane is required for use with this module.
2.2.3 Power Requirements
The ADM-VPX3-9V2 draws power from only VS1 (12V) and the 3.3V auxiliary power. All other power rails are
unused and unconnected.
Power consumption estimation requires the use of the Xilinx XPE spreadsheet and a power estimator tool
available from Alpha Data. Please contact support@alpha-data.com to obtain this tool.
The power available to the rails calculated using XPE are as follows:
Voltage
Source Name
Current Capability
0.85-0.90
V VCC VCC_BRAM
105A
0.9
MGTAVCC
7A
1.2
MGTAVTT
12A
1.2
1V2_DIG (DDR4)
12A
1.8
VCC VCCO_1.8V
5.5A
1.8
MGTVCCAUX
1A
3.3
3.3V (FireFly and logic ICs)
5A
Table 2 : Available Power By Rail
Page 4
Board Information
ad-ug-1377_v1_2.pdf
