ADM-VPX3-9Z2 User Manual
V1.1 - 16th January 2020
3.4 JTAG Interface
3.4.1 On-board Interface
A JTAG boundary scan chain is connected to header J2. This allows the connection of the Xilinx JTAG cable.
Figure JTAG Boundary Scan Chain
:
FPGA
XCZUxxEG
FFVB1156
FMC+
I/F
PRESENT#
VREF (3.3V)
Buffer
3.3V
En#
FMC_TDI
FMC_TDO
HDR_TDI
HDR_TDO
Buffer
3.3V
En#
VPX
Con
(P0)
Header
J2
VPX_TDI
VPX_TDO
VPX_JTAG_EN#
SW3-5
Figure 4 : JTAG Boundary Scan Chain
If the boundary scan chain is connected to the interface at the VPX backplane (SW3-5 is ON), header J2 should
not be used.
3.4.2 VPX Interface
The JTAG interface on the VPX backplane is normally unused. When SW3-5 is OFF (default), all JTAG signals to
P0 are left floating.
The JTAG interface can be connected to the VPX Backplane (through level-translators) by switching SW3-5 ON.
3.4.3 JTAG Voltages
The on-board JTAG scan chain uses 3.3V. The Vcc supply provided on J2 to the JTAG cable is +3.3V and is
protected by a poly fuse rated at 350mA.
The JTAG signals at the VPX interface use 3.3V signal levels and are connected through buffers to the on-board
scan chain.
The JTAG signals at the FMC interface also use 3.3V signal levels and are connected through buffers to FMC
boards scan chain.
Page 10
Functional Description
ad-ug-1323_v1_1.pdf
