Alpha Micro AM-210, Technical Manual

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Page 2: ... alpha n1ICrO TECHNICAL MANUAL FOR AM 21 0 FLOPPY DISK CONTROLLER CIRCUIT BOARD Manufactured By ALPHA MICROSYSTEMS 178B1 SKY PARK NORTH IRVINE CALIFORNIA 8271 4 ...

Page 3: ...ed or having possession thereof by acceptance assumes custody thereof and agrees that the doc ument Is given in confidence and will not be copied or reproduced in whole or In part nor used or revealed to any person In any manner except to meet the purposes for which It was delivered Additional rights and obligations regarding this document and Its contents may be defined by a separate written agre...

Page 4: ...ENCE FROM NAME NOTE Use this form to communicate any errors ADDRESS suggested changes or general comments about this document If necessary ca II us at CITY 714 957 6076 STATE ZIF DOCUMENT TITLE NUMBER REVISION_ COMMENTS FOLD STAPLE MAIL ZZ F a0002 1 ...

Page 5: ...FOLD FOLD I I I I I I I I I alpha 4 lcra 17BRl Sky Park North Irvine California tJ2714 ATTN EDUCATIONAL SERVICES DIVISION PLACE STAMP HERE FOLD FOLD I I I I I I I I I I I I I I I w 2 J J 2 o J t t J U ...

Page 6: ...cations 2 1 Interface Description and Wiring S 100 Bus Inter ce Floppy Drive Interface User Options 2 1 2 1 2 1 2 6 2 9 Bootstrap Header Option I O Port Address 2 9 2 9 2 9 Master Clock Frequency Option Vectored Interrupt Option 2 9 Seek Complete Interface Line Option 2 10 Software Control Step Rate Option 2 10 Data Separator Timing Opt n 2 10 Write Pre Compensation Options 2 11 SECTION 3 PROGRAMM...

Page 7: ...Port Bootstrap Circuitry I O Address Circuitry Command Generator RAM and Control Circuitry ternal Status and Control Registers Data Clock Separator Write Pre Compensation PRDY Control Logic 4 18 4 18 4 18 4 19 4 19 4 19 4 20 4 20 4 22 4 22 DRQ Processor 4 23 Circuit Module Description 4 25 Floppy Disk Formatter Controller Description CUI 4 25 Organization 4 30 Processor Interface 4 33 Floppy Disk ...

Page 8: ...4 60 4 63 4 66 BCD Decimal Decoder Driver U13 Tri State Buffers U16 4 68 4 69 Bus Comparator U25 U26 4 70 D Positive Edge Triggered Flip Flops with Preset and Clear U12 4 71 Tri State Oct al Buffers U36 I 4 71 Tri State Buffers U39 Dual J K Negative Edge Triggered Flip Flops With Preset UB Dual Retriggerable One Shots with Clear U14 UIS Decoder U29 Data Selector Multiplexer U17 4 72 4 72 4 73 4 74...

Page 9: ...oard Checkout Warranty Procedures Troubleshooting Procedures Operational Test 5 1 5 1 5 2 5 2 5 2 Diagnostic Procedures 5 3 Ini tial Register Check eDDTST 5 4 Floppy Controller Chip Test 1791T 5 6 Floppy Drive Seek Test and Data Separator Calibration SEEK 5 7 Floppy Interface Drive Test FTST 5 11 Evaluation Procedure 5 16 SECTION 6 SCHEMATIC AND PARTS LIST iv ...

Page 10: ...ow Type III Command Write Track 4 41 4 47 4 53 IBM Track Format Read Enable Timing 4 57 4 60 4 11 Write Enable Timing 4 61 4 12 Input Data Timing 4 62 4 13 Miscellaneous Timing 4 62 4 14 Static RAM Connections 4 63 4 15 RAM Read and Write Timing 4 64 4 16 8K UV Erasable PROM Connections 4 66 4 17 8K UV Erasable PROM Timing 4 66 4 18 Decoder Driver Logic and Connections 4 68 4 19 Trl State Buffer C...

Page 11: ...ri State Inverter Bu r Connections Tri State Buffer Connections Page 4 73 4 74 4 75 4 76 4 76 Four Bit Binary Ripple Counter Connections 4 77 Volt Controller Oscillator Connections 4 78 Tri ate D FI ip Flop Connect ions 4 79 4 Bit Binary Counter Connections 4 80 Logic Delay Module Diagram and Connections 4 81 PROM Connections and I O Circuits 4 82 D Flip Flop Connections 4 83 vi ...

Page 12: ...ter No 2 Functions X7 3 5 AM 210 Signals List 4 4 S 100 Bus Interface Signals List 4 11 AM 210 Floppy Disk Interface Signals List 4 14 Floppy Disk Formatter Controller Signal List 4 26 AM 210 Regi s ter Addre s s es 4 30 Stepping Rates 4 35 4 40 4 43 Command Summary Flag Summary Type I Commands Flag Summary Type II Commands 4 46 Control Bytes For Initialization 4 52 Status Register Summary 4 55 St...

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Page 14: ...k transfers of d a tab e t wee nth e s ys t em and up toe i gh t flo p Py dr i ve s ARe adOn1 y Me1111 ROM is contained on the board to provide an optional boot load prograJ A simplified block diagram of the circuit board is shown in Figure 1 1 For a complete detailed description of circuit board operation see Section 4 of this manual 1 2 APPLICATION The AM 210 is fully compatible with the standar...

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Page 16: ...tween floppy disk drives and system memory under CPU control Specifications for the AM 210 circuit board are contained in Table 2 1 2 2 INTERFACE DESCRIPTION AND WIRING The AM 210 Floppy Disk Controller provides interface capability between the standard S 100 Bus and floppy disk drives 2 2 1 5 100 BUS INTERFACE The AM 21D circuit board is fully 5 100 Bus compatible The board and its associated flo...

Page 17: ...ht drives can be controlled by one AM 2ID circuit board Eight I O ports utilized for data and control Accommodates single and double density formats IBM 3740 Single Density PM IBM 34 Double Density MFM Compatible with single or double sided disks Variable step rate including sriftware programmable 8 x 1024 bit PROM containing bootstrap program Jumper block provides for boot no boot option Multiple...

Page 18: ...loppy configu rations Write Contains write precompensation circuitry Precompensation that is jumper selectable for delays from 50 to greater than 500 nanoseconds 1emory Control SoftvJare control of PROM and system memory contained in the same address space Table 2 2 100 Bus Interface Signals List MNEMONIC fJAHE PIN AO Address 0 79 A1 Address 1 80 A2 Address 2 81 A3 Address 3 31 1 4 Address 4 30 A5...

Page 19: ... Data Bit 3 42 DATAIN 4 Input Data Bit 4 91 DATAIN 5 Input Data Bit 5 92 DATAIN 6 Input Data Bit 6 93 DATAIN 7 Input Data Bit 7 43 DATAOUT 0 Qutput Data Bit 0 36 DATAOUT 1 Output Data Bit 1 35 DATAOUT 2 Output Data Bit 2 88 DATAOUT 3 Output Data Bit 3 89 DATAOUT 4 Output Data Bit 4 38 DATAOUT 5 Output Data Bit 5 39 DATAOUT 6 Output Data Bit 6 40 DATAOUT 7 Output Data Bit 7 90 PDBIN Data Bus In 78 ...

Page 20: ...SINP I O Input Cycle 46 SOUT I O Output Cycle 4S I VIa Interrupt 0 4 VII Interrupt 1 S VI2 Interrupt 2 6 VI3 Interrupt 3 7 VI4 Interrupt 4 B VIS Interrupt S 9 VI6 Interrupt 6 10 VI7 Interrupt 7 11 2 Phase 2 clock 24 8VDC 8VDC 1 51 16VDC 16VDC Z 16VDC 16VDC 52 GND Ground SO 100 2 5 _ ...

Page 21: ... length must not exceed 20 feet Standard B floppy drives interface through J2 and 5 mini drives interface through J3 Floppy drive interface signals are listed in Table 2 3 For a complete description of these signals and theit operation 1n the AM 210 see Section 4 1 of this manual Table 2 3 AM 210 Floppy Disk Interface Signals List 1NEMONIC HAME PIN J2 J3 DSO Drive Select 0 26 10 Rtn 25 9 DSl Drive...

Page 22: ...0 8 Rtn 19 7 INWARDS Direction Select 34 18 Rtn 33 17 MOTORON Motor On 16 Rtn 15 RDATA Disk Output Data 46 30 Rtn 45 29 READY Ready For Drive Selected 22 Rtn 21 SEEK COMPLETE Seek Operation Complete 12 Rtn 11 SEPCLOCK Separated Clock SO Rtn 49 SEPDATA Separated Data 48 Rtn 47 SIDESEL Side Select 14 32 Rtn 13 31 2 7 t 0 ...

Page 23: ... MNEMONIC NAME PIN J2 J3 STEP Step Pulses 36 20 Rtn 35 19 TG43 Track Greater Than 43 2 Rtn 1 TRACK 0 Track 0 42 26 Rtn 41 25 TWOSIDED Two Sided Disk 10 Rtn 9 WDATA Write Data 38 22 Rtn 37 21 WG Write Gate 40 24 Rtn 39 23 WP Write Protect 44 28 Rtn 43 27 2 8 ...

Page 24: ... operation 7 2 3 2 1 0 PORT ADDRESS The I O address is placed in circuit etch for FO This can be easily altered by cutting the appropriate address header line and jumpering it to either the 5 volt or ground pad provided 2 3 3 STER CLOCK FREQUENCY OPTION To allow for the controller chip U1 to function in either a standard or mini floppy configuration the master clock fre quency is jumper selectable...

Page 25: ...h epad 1abe1 e d SS 2 3 7 DATA SEPARATOR TIMING OPTION To accommodate both 5 and 8 floppies in both a single and double density format two options are provided 1 Phase lock oscillator PLO frequency control option To provide for chip to chip variations in the 74LS324 trim pot R39 can be added in place of RIO Ril This is typically factory chosen and set and should not be changed unless U2 is replace...

Page 26: ... can be selected by jumpering appropriate pads for the selected delay time The actual delays are varied by jumpering one of the outputs of U6 labeled 50 250 to either the E L or T pads at U17 The standard set up allows for 150 oSee jumpered to T etched circuitry 250 nSec jumpered to L and E jumpered to B for no delay Note that the 05 version board utilizes a delay module in which these times are d...

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Page 28: ...t I O ports are required by the AM 210 controller as described in Table 3 1 Note that the first four I O addresses are con tained in the floppy controller Ie Ul See paragraph 4 2 1 for more detailed information on the floppy controller module 3 2 EXTERNAL CONTROL REGISTERS In addition to the registers contained in the floppy control module there are other registers which must be programmed for pro...

Page 29: ... Sector See FD1791 spec Register Register attached X3 Data Data See FDl791 spec Register Register attached X4 RAM Port RAM Port I O port access for 1024 byte on board RAM XS Reset RAM address Register X6 External Status External Control See Table II Register Register 1 X7 External Control See Table III Register 2 I O Port Address is jumper programmable to any ven block of eight I O addresses 3 2 ...

Page 30: ...ite operations 1 Select Drive 1 2 Select Drive 2 3 Select Drive 3 4 Select Side 1 Side 0 is standard 5 Motor ON Controls mini floppy motor drive 6 Step Command Can be used to control floppy disk track stepping rate instead of using the STEP signal from FD1791 7 Double Density Mode Selects Double Density mode of operation 3 3 I ...

Page 31: ...tatus register This bit is a copy of the interrupt signal from the FD1791 It can be used by processors which are not interrupt driven to sense when a command has been completed When high indicates single drive Indicates drive has not completed seek command option only Note This register may be READ without affecting any command which may be in progress excluding WRITE TRACK During a READ or WRITE ...

Page 32: ...et this bit disables the on board Bootstrap PROM and enables any system memories controlled by the Phantom line Indicates to the internal I O logic whether to read from or write to the floppy drive When set block I O data transfers are expected to the Data Register in the FD1791 The controller by holding PRDY will control the data rate from the processor 3 5 ...

Page 33: ...I O port X4 will automatically increment the RAM address register and provide the next byte of data 4 When reading is complete reset the RAM address register to zero as in Step 1 In order to write into the on board RAM buffer the following sequence of operations must take place 1 The RAM address must be reset to zero output command to I O port X5 Issue an 2 Write to I O port X4 to write the first ...

Page 34: ...When the floppy drive has received all the required data it sets tne interrupt bit and writing ceases Even if more than the required data is transferred to the Data ReSister it only sends to the floppy drive what is required When the External Status Register is checked for Bi t IJo 1 true the transfer is complete The Interrupt Bit is tnen reset when the module Status Register is next read for the ...

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Page 36: ... information for each of the integrated circuit elements 4 1 CIRCUIT BOARD OPERATION This circuit board provides control and interface capability between the S 100 Bus and most popular floppy disk drives The functional block diagram of the circuit board is shown in Figure 4 1 and the circuit board schematic is contained in Section 6 of this manual Table 4 1 contains a list of the signals used in t...

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Page 38: ...on the address block BINTR Board Interrupt Request 6 Floppy controller module output set at the completion of any operation and reset when a new command is loaded into the module command register or the module status register is read CE Chip Enable 3 Formatter controller module input for chip select to enable the module eLK Clock 5 1 Mhz or 2 Mhz system clock depending on jumper to U9 CRAMCS RAM c...

Page 39: ...ter Controller module output to indicate that the wri te data pulse occurring while EARLY is active high should be shifted early for write precompensation FORMAT Format 6 Output of external control register 2 from DATAOUT bi t 3 When asserted block I O data transfers are expected HLD Head Load 6 Output to cause the disk to be placed in close proximity to the Read Write head HLT Head Load Timing 6 ...

Page 40: ...put to load External Control Register 2 U35 from CPU output data BDOUTO 7 LDRAM Load RAM 3 Write enable to RAM U30 U31 generated from LDRAMI from the command generator or from RAMWR from the DRQ processor LDRAMI Load RAM 1 3 Command Generator output to generate LDRAM to wri te data into the AM 2ID Random Access Memory LOBDSEL Low Board Sele t 3 Selects the registers internal to the Formatter Contr...

Page 41: ...phased to the RD 4TA input fi1lATA Read Data I 6 Formatter Controller nodule data input directly from the disk drive fegative pulse for each recorded flux tran i tion RUeR Read Status Register 3 Output of the command generator to enable the external status register to transfer data to DArIN 0 3 RDRAMl Read RAM 3 Reads AM 210 Random Access femorf RG Read Gate 6 t ot used RSTAR Reset RAM Address Reg...

Page 42: ... Controller module output to inform the drive that the Read Write head is positioned between 44 76 Output valid only during read and write commands WD Wri te Data 6 Write Data output of the Formatter Controller module Contains address marks as well as data WDAO Module Address O 3 Formatter Controller module address line zero for accessing the active registers with active CE WDRE and WDWE WDAI Modu...

Page 43: ...odule input to set the write mode with active chip select EE signals WG Write Gate 6 Write gate output of Formatter Controller module to floppy disk drive WR Wri te Strobe 3 AM 2IO signal driven by 5 100 Bus signal PWR generated by bus masters as write command to slaves WRTFLOPPY Write flopPY 6 External control register output from DATAOUT2 indicating whether to read from or write to the floppy dr...

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Page 45: ...TAIN 0 Input Data Bit 0 95 Data Input Port DATAIN 1 Input Data Bit 1 94 Bus Master Input from DATAIN 2 Input Data Bit 2 41 Slaves DATAIN 3 Input Data Bit 3 42 DATAIN 4 Input Data Bit 4 91 DATAIN 5 Input Data Bit 5 92 DATAIN 6 Input Data Bit 6 93 DATAIN 7 Input Data Bit 7 43 DATAOUT 0 Output Data Bit 0 36 Data Output Port DATAOUT I Output Data Bit 1 35 Bus Master Output to DATAOUT 2 Output Data Bit...

Page 46: ...11 4 12 DESCRIPTION Read enable Used by bus master to request addressed slave to place data on input port Disables phantom controlled memories when asserted AM 2ID I O signal to allow extensions of bus timing Write strobe generated by bus masters as write command to slaves AM 2ID reset input from bus AM 2ID I O signal indicating I O input operation Current bus cycle is a bus master input from a me...

Page 47: ...S 100 Bus Interface Signals List MNEMONIC NAME PIN DESCRIPTION 2 Phase 2 clock 24 Phase 2 clock from CPU 8VDC 8VDC 1 8V power 51 16VDC 16VDC 2 16V power 16VDC 16VDC 52 16V power GND Ground 50 Sys tern Ground 100 4 13 ...

Page 48: ... drive No O 12 AM 21D output selects 11 disk drive No 1 14 AM 21D output selects 13 disk drive No 2 6 AM 21D output selects 5 disk drive No 3 AM 210 output A low active signal causes the read write head to load against the disk provided READY is active 8 AM 21D input One ms 7 negative going pulse occurs for each revolu tion of the selected disk 18 AM 2ID output Defines 17 direction of motion of th...

Page 49: ... 15 16 15 30 AM 210 input Clock and 29 data output of selected head Each flux transi tion produces negative pulse AM ZIO input A low level indicates that a diskette is loaded in selected drive and is within 90 of its operating speed AM ZIO input Low level indicates that a seek or restore operation has been completed jumper connec tion in AM 2IO AM ZIO input Separated clock data from read data jump...

Page 50: ...s side 1 surface for reading and writing and a high signal selects side o 20 AM 2I0 output Low level 19 of one pulse for each track crossed by the head for a seek to a new address AM 2ID output Active low reduces writing cur rent when on tracks 44 76 26 AM 2ID input Low level 25 indicates heads are posi tioned over track o AM 2ID input indicates a two sided diskette is rotating in the drive 22 AM ...

Page 51: ...ace Signals List MNEMONIC NAME PIN DESCRIPTION J2 J3 WG Write Gate 4D 24 AM 2ID output Low level Rtn 39 23 turns on write current WP Write Protect 44 28 AM 2ID input Low level Rtn 43 27 indicates that the selected disk is write protected 4 17 ...

Page 52: ... tri state buffers to interface the AM 2l0 circuit board with CPU input data One set of buffers interfaces the internal tri state bus DALO 7 to transfer data from the internal RAM or the floppy controller module These buffers are gated by logic in the command generator The other part of the data in port is the external status register that transfers status information to the system data bus DATAIN...

Page 53: ...nd any activity to from the floppy controller module 4 1 5 COMMAND GENERATOR This octal register decodes the activity of the board via address lines AO AI A2 and the bus master input SINP When the CPU is outputting to the AM 2l0 SINP is high and the selectable operations are 1 Resetting the RAM address register RSTAR 2 Loading the RAM CLDRAMl 3 Loading the control register CLDCRl LDCR2 When SINP i...

Page 54: ...p Rates that cannot be provided by the floppy controller module External Control Register No 2 provides the on board logic circuitry with selection of the Format mode Phantom memory disable Interrupt Enable and the Write to Floppy mode This register is loaded from the LDCR2 command from the command generator Port X7 The External Status Register provides 4 bits of information back to the Processor ...

Page 55: ...d Slow down range that the oscillator maintains in order to lock to the data signal This allows for maximum data transfer with minimal lost data This circuitry also includes a tuned low pass filter as well as a linear opera tional amplifier for noise isolation See Figure 4 2 for the data separator timing 200 N SEC TVP RDATA JITTER BAND I NOTE TYPICAL JITTER OCCURS ON RDATA FROM MUlTI REAOS f DISK ...

Page 56: ...ximum delay or on time theoretically no delay but typically 150 nSec 4 1 10 PRDY CONTROL LOGIC This circuitry provides for the timing variations among floppy drives and the actual processor set During formatting the actual data transfer rate is governed by tbe need for the floppy controller module for more data As the timing diagra in Figure 4 3 indicates any board activity to ttle floppy controll...

Page 57: ... Processor and BDRQ request for data When BINTR is sent Active Hight PRDY is sent in the inactive state high Even if additional BDRC are generated the controller module h interrupted out and will not write additional data BINTR remains Active high until the Status Register of the floppy controller moduli is read The format bit is then reset high and the process complete i 4 1 11 DRO PROCESSOR This...

Page 58: ...t address s e 1 e c t ion 0 f the ROM a11 0 ws for RAM wl i teo f t rI e mod u1 e da t a Aft e r the last DRQ nd the controller module has interrupted out BINTR set the octal flipflop U43 is disabled and the DR processor is esserltially stopped The write mode is similar The signals controlled are RAl 1 chip select HAMeS RAM write RAM R and module read enable WDRE2 and write enable WDWE nuary 1980 ...

Page 59: ... the data accessing controls and the bidirectional transfer of informa tion between the processor s memory and the magnetically stored data on the diskette The diskette data can be stored in a data entry format compatible with the IBM 3740 single density or IBM System 34 double density formats In either format all information is recorded on tracks c radial paths in sectors arc sections defined by ...

Page 60: ...th the device Initiates the Read mode to search for a track and sector code in the ID field equal to that in the track and sector registers Register address line 0 for accessing the active registers with CS RE and WE See Table 4 5 Register address line 1 for accessing the active registers with CS RE and WE See Table 4 S Data Access Lines Bits 0 7 Step motor control that contains a pulse for each s...

Page 61: ...device and loads hex 03 into the command register The Not Ready Status Bit 7 is reset during MR ACTIVE When MR is brought to a logic high a Restore Command is executed regardless of the state of the Ready signal from the drive Also hex 01 is loaded into sector register Ground SV power input For testing only A logic high indicates that the read write head is engaged Jumper selected clock A high lev...

Page 62: ...ause the storage element to be placed in close proximity to the Read Write head This output informs the drive that the Read Write head is positioned between the 44 76 This output is valid only during Read and Write Commands Write Gate output to floppy disk drive A 250 ns MFMJ or 500 ns PM pulse per flux transition WD contains the unique Address marks as well as data in both FM and MFM formats This...

Page 63: ...nput signal to indicate when the index mark is encountered once per revolution of the disk This input is sampled whenever a Write Command is received A logic low terminated the cOIIHnahd an set thewr i te Protect Status bit This pin selects either single or double density operation When DDEH O double density is selected When DDEN l single density is selected This open drain output indicates that t...

Page 64: ...e Write Data output during Write operations Data Register This 8 bit register is used as a holding register during Disk Read and Write operations the assembled data byte is transferred Register from the Data Shift Register information is transferred in parallel to the Data Shift Register In Disk Read operations in parallel to the Data In Disk Write operations from the Data Register When executing ...

Page 65: ...RlttAMIl 1i Ofi o COWt uTfA INTERFACE CONTAOl Figure 4 5 CONTROL PlA COfnAOl OISI COtolTROl IIiIITERFAct 12 10 I COIilTAOL Floppy Disk Formatter Controller Module Block Diagram 4 31 ItCLIl WG STATUS 10 TG43 WPRT WF jJ 1 1 100 READY STEp DIRC EARLY LATE RG HLO HiT ...

Page 66: ...e loaded when the device is busy Command Register CR This a bit register holds the command presently being executed This register should not be loaded when the device is busy unless the execution of the current command is to be overridden This latter action results in an interrupt The command register can be loaded from the DAL but not read onto the DAL Status Register STR This 8 bit register hold...

Page 67: ...rocessor is accomplished through the eight Data Access Lines DAL and associated control signals j The DAL are used to transfer Data Status and Control words out of or into the module The DAL are three state buffers that are enabled as output drivers when Chip Select CS and Read Enable RE are active low logic state or act as inpnt receivers when CS and Write Enable WE are active When transfer of da...

Page 68: ...ata Request is activated when the Data Register transfers its contents to the Data Shift Register and requires a new data byte It is reset when the Data Register is loaded with new data by the processor If new data is not loaded at the time the next serial byte is required by the Floppy Disk a byte of zeroes written on the diskette and the Lost Data bit is set in the Status Register At the complet...

Page 69: ...if the E flag is set in any Type 2 or 3 command See paragraph 4 2 1 9 for a descrip tion of command types The rates shown in Table 4 6 can be applied to a Step Direction Motor through the device interface Table 4 6 Stepping Rates OlK 2 MHz 2 MHz 1 MHz 1 MHz 2 MHz 1 MHz i556i 0 0 x At AO T EiT TEST T EiT 1 TiiT TESTaO TESTaO 0 0 3 ml 3 ml IS ml IS ml A ppro Appro 0 1 8 ml IS ml 12 ml 12 m 400 1 0 1...

Page 70: ... INTRQ is generated The Head Load HLD output controls the m0vement of the read write head against the media HLD is activated at the beginning of a Type 1 command if the h flag is set h 1 at the end of the Type 1 command if the verify flag V 1 or upon receipt of any Type II or III command Once HLD is active it remains active until either a Type I command is received with h 0 and V 0 or if the modul...

Page 71: ... HLD is made active an internal 15 ms delay occurs and then HLT is sampled until true 4 2 1 6 DISK READ OPERATIONS Sector lengths of 128 256 512 or 1024 are obtainable in either PM or MPM formats For FM DDEN should be placed to logical 1 For MFM formats DDEN should be placed to a logical O ft Sector lengths are determined at format tim by a special byte in the IDu field If this Sector Length byte ...

Page 72: ...m Similarly for MFM RG is made active true when 4 bytes of OOtt or ttFpft are detected The module must find an address mark within the next 16 bytes otherwise RG is reset and search resumes 4 2 1 7 DISK WRITE OPERATION When writing is to take place on the diskette the Write Gate CWG output is activated allowing current to flow into the Read Write head As a precaution to erroneous writing the first...

Page 73: ... is to be written at nominal Since write pre compensation values vary from disk manufacturer to disk manufacturer the actual value is determined by several delay linei which are located external to the module The write pre compensation signals EARLY and LATE are valid in both FM and MFM formats Whenever a Read or Write command Type lIar III is received the module samples the Ready input If this in...

Page 74: ...0 1 h V rl ro I Step a 0 1 u h V fl rn I Step In 0 1 o u h V fl ro I Step Out a 1 1 u h V I ro II Read Sector 1 0 0 m X E a 0 II Write Sector 1 0 1 mX E X ao III Read Address 1 1 0 o 0 1 0 0 III Read Track 1 1 1 o 0 1 o X III Write Track 1 1 1 1 0 1 o 0 IV Force Interrrupt 1 1 0 1 11 12 IJ 10 x Don t care Note Bits shown in TRUE form 4 2 1 9 TYPE I COMMANDS The Type I Commands include the Restore ...

Page 75: ...Figure 4 6 Type I Command Flow Sh 1 of 2 4 41 ...

Page 76: ... on JFTlSl C THfAl IS WS DELA if fro A O Cl II fAf IS A lOWS Oft AY Figure 4 6 Type I Command Flow Sh 2 of 2 4 42 ...

Page 77: ...lag Summary Type I Commands h Head Load Flag Bit 3 h 1 Load head at beginning h 0 Unload head at beginning V Verify flag Bit 2 V 1 Verify on last track V 0 No verify rir O Stepping motor rate Bits 1 0 Refer to Table 4 for rate summary u Update flag Bit 4 u 1 Update Track register u 0 No update The Type I Commands also contain a verification V flag which determines if a verification operation is to...

Page 78: ...ster is not updated Restore Seek Track 0 Upon receipt of this command the Track 00 TROO input is sampled If TROO is active low indicating the Read Write head is positioned over track 0 the Track Register is loaded with zeroes and an interrupt is generated If TROQ is not active low stepping pulses pins 15 to 16 at a rate specified by the rir O field are issued until the TROO input is activated At t...

Page 79: ...he h bit allows the head to be loaded at the start of the command An interrupt is generated at the completion of the command Step in Upon receipt of this command the module issues one stepping pulse in the direction towards track 76 If the u flag is on the Track Register is incremented by one A er a delay determined by the rIrO field a verification takes place if the V flag is on The h bit allows ...

Page 80: ...oaded and HLT sampled with no 15 msec delay The ID field and Data Field format are shown below GAP 110 I TRACK I SIDE ISECTOR ISECTOR CRC CRC IGAP IDATA III AM NUMBER NUMBER NUMBER LENGTH 1 2 II AM ICRC I CRC DATA FIELD 1 2 10 FIELD DATA FIELD In MFM only lOAM and DATA AM are preceded by three byt of A1 with clock transitfon between bits 4 and 5 missing Table 4 9 Fl Summary Type II Commands TYPE I...

Page 81: ... NOn irlffi 0 T EAf IS NO I ototS DELAY 1rTfn AND eu tlolfAE IS IUS DHA Figure 4 7 SET TG 43 Type II Command Flow Sh 1 of 2 4 47 INTRO AEUT BUSY SIET AfCORO IIfOT IOUND ...

Page 82: ...Figure 4 7 INTRO JlESET eus SET M CMl HOT FOUND Typ II Command Flow Sh 2 of 2 4 48 SET OATA LOST WflITEeVTE 01 ZEROS ...

Page 83: ...be read or written depending upon the command If m 0 a single sector is read or written J and an interrupt is generated at the completion of the command If m 1 multiple records are read or written with the sector register internally updated so that an address verification can occur on the next record The module continues to read or write multiple records and update the sector register until the se...

Page 84: ...field is recorded in the Status Register Bit 5 as shown below STATUS BIT 5 1 o Deleted Data Mark Data Mark Write Sector Upon receipt of the Write Sector command the head is loaded HLD active and the Busy status bit is set When an ID field is encountered that has the correct track number correct sector number and co rect eRC a DRQ is gen erated The module counts off 11 bytes in single density and 2...

Page 85: ...ext encountered ID field is then read in from the disk and the six data bytes of the ID field are assembled and transferred to the DR and a DRQ is generated for each byte The six bytes of the ID field are shown below TRACK slOe SECTOR SECTOR CRC CRe ADOA NUMBER ADDRESS LENGTH 2 2 2 3 5 6 Although the CRe characters are transferred to the computer the module checks for validity and the eRC error st...

Page 86: ...lized when any data byte from F8 to FE is about to be transferred from the DR to the DSR in FM or by receipt of FS in MFM See Figure 4 8 for flow diagrams for Command Write Track Table 4 10 Control Bytes for Initialization DATA PATTERN IN DR HEX 00 thru F4 F5 F6 F7 F8 thru FB FC FD FE FF FD1791 INTERPRETATION IN FM DDEN 1 Write 00 thru F4 with Clk FF Not Allowed Not Allowed Generate 2 CAe bytes Wr...

Page 87: ...Figure 4 8 Type III Command Write Track 4 53 WRITE 2 CAC CHAAS cue WRITE FC elK O WAITE FO FE OR FI 8 ClM C1 INITIALIZE CRe WRln a ITlE OF nllos sET DATA LOST ...

Page 88: ...is terminated and busy is reset This is the only command that will clear the immediate interrupt 4 2 1 13 STATUS DESCRIPTION Upon receipt of any command except the Force Interrupt command the Busy Status bit is set and the rest of the status bits are updated or cleared for the new command If the Force Interrupt Command is received when there is a current command under execution the Busy status bit...

Page 89: ...IT NAME S7 NOT READY S6 PROTECTED MEANING This bit when set indicates the drive is not ready When reset it indicates that the drive is ready This bit is an inverted copy of the Ready input and logically ored with MR When set indicates Write Protect is activated This bit is an inverted copy of WRPT input 55 HEAD LOADED When set it indicates the head is loaded and engaged This bit is a logical and o...

Page 90: ... not respond to DRO in one byte time This bit is reset to zero when updated This bit is a copy of the DRO output When set it indicates the DR is full on a Read Operation or the DR is empty on a Write operation This bit is reset to zero when updat d When set command is under execution When reset no command is under execution 4 2 1 14 FORMATTING THE DISK Refer to Figure 4 8 for Type III ow diagrams ...

Page 91: ...tern will generate two eRC characters in FM or MFM As a consequence the patterns F5 thru FE must not appear in the gaps data fields or ID fie1 ds Also eRe s must be generated by an F7 pattern Dis ks may be formatted in IBM 3740 or Sys tern 34 formats wi th sector lengths of 128 256 512 or 1024 bytes See Figure 4 9 for IBM Track format MOOt I t JW IYln CJ j H w 00 G Ol DGU I w 1 1 O f O Ill cOllO 1...

Page 92: ...TE WRITTEN FC Index Mark FF 00 FE 10 Address Mark Track Number 00 Sector Number 1 thru 1A 00 F7 2 CRC s written FF 00 FB Data Address Mark Data I BM uses E5 F7 2 CRCts written FF FF Write bracketed field 26 times Continue writing until module interrupts out Approx 247 bytes 4 2 1 16 IBM SYSTEM 34 FORMAT 256 BYTES SECTOR Shown below is the IBM dual density format with 256 bytes sector In order to f...

Page 93: ...until module interrupts out Approx 598 bytes 4 2 1 17 NON IBM FORMATS Variations in the IBM format are possible to a limited extent if the following requirements are met sector size must be a choice of 128 256 512 or 1024 bytes gap size must be according to the following table Note that the Index Mark is not required by the module FM MFM Gap I 16 bytes FF 16 bytes 4E Gap II 11 bytes FF 22 bytes 4E...

Page 94: ... Timing _ CHARACTERISTIC MIN TYP MAX Setup ADOR CS to RE 0 Hold ADOR CS from RE 10 AE Pulse Width 500 OAa Reset from RE 40 J 500 INTRa Reset from RE 500 3000 Data Access from RE 350 Data Hold From RE 50 150 _____ L 8 OR 11 I I vOL All CS _ _ v l lIr of _ V H 0 TA VALID IInti RfiAO OAT tBUH AS TAt_ SU TE DI OT I 12 81 PfIllWAI It TL T fO Lo OfS EO TIMI DOUkES CLDCa Iu t S RVICE WOAST CASE FM 275 5 ...

Page 95: ... 500 3000 Data Setup to WE 250 Data Hold from we 20 101 110 1 II ________ SUr J I i os I 0 1 0 iN I OA 10 4t IoIO f AII e P R ANE TLV f fO LOW I OESII IIO 1 WH E _ T ING OA1 INTI SEC TO IACII OR OJ TA EO SI II uUA CANNOT AUO TH S AfQ SfEA UN A lEAST S C N FUI I TH I I SII IO EDell O WE SERVICE IWOAST CASE _ENWIIII INGI OTHECO NO EOIST AS A US u 3 s fU isS U E I 1 oouellS Hflll CLOCIt tWHl Figure 4...

Page 96: ...D HOT COHeE HIMSII I WHETHI THISE lIU AlliE Cl c1C 0111 DATA THE fDl WILL ASCEIilTAI THIS 0111 I OTWEll WOIID ClI hlAV BE INYE TED NOMINAL DISKETTE MODE OOEN elK T T T 8 MFM 0 2 MHz 1 pi 11JS 2p a 8 FM 1 2 MHz 2p a 2pl 4 pi 5 MFM 0 1 MHz 2ps 2pl 4p a 5 FM 1 1 MHz 4 uJ 4 pi 8 S Figure 4 12 Input Data Timing MIN 230 200 2 or 4 12 50 10 10 4 62 TYP MAX UNITS CONDITIONS nsec nsec Sec lAec See Note sec...

Page 97: ...e when elK 1 MHz 4 In MFM the EARLY and LATE signals are valid at least 125 ns from either edge of WD 4 2 2 1024 x 4 BIT STATIC RAM U30 U31 Th device is a 4096 bit static Random Access Memory RAM organized as 1024 words by four bits It uses fully DC stable s tatic circui try throughout and requires no clocks or refresh ing to operate The data is read out nondestructively and has the same polarity ...

Page 98: ... CYCLE IWC x I _ _ _ _ _ ADDRESSJ X __ ono DOVT NOTES D Wlil hiGh for a Reed Cycle 2 tw is m ured from thellu r of C or W OOinglow to Wl going high Q W mutt 1 I gh during all addr tranlition twR is r flrenced to the high tr ntition of WI o W Figure 4 15 RAM Read and Write Timing 4 64 ...

Page 99: ...f CS low and WE low To prevent the loss of data the addresses must be properly established during the entire Write time plus twRa Internal delays on the 2114 are established such that address decoding propagates ahead of data inputs keyed by the Write time Therefore it is permissable to establish the addresses coincident to the selection of a Write time but no later If the Write time precedes the ...

Page 100: ... CON IfCn D TO Iss FO THE 27114 PIN NAM S AG 0 1 BLOCK DIAGRAM V DECODER Al __________ DECODE OArA output UO 07 I v GATING PIN CONNECTION DURING READ OR PROGRAM PIN NUMBER ADDRESS I T Vas1 lice OATA 1 0 INPUTS I 91f 18 vss j PROGRAM 1100 CSIWE MODE 13 n 22 23 12 l8 19 26 21 24 READ Dout A II GND GND 12 V 5 I 5 I DESELECT MIOM IMPEDANCE DON T CARE GND GND 12 V 1 5 PROGRAM 0 A GIllD I PULSED 12 V HW...

Page 101: ... have wavelengths in the 3000 4000A range Data show that constant exposure to room level fluorescent lighting could erase the typical device in approximately 3 years while it would take approximately 1 week to cause erasure when exposed to direct sunlight If this device is to be exposed to these types of lighting conditions for extended periods of time opaque labels are available which should be p...

Page 102: ...I II It II 4 r P I f I I 1 r e IUMB Truth Table lwun OUTPUrI NO I D C A D 2 I 4 1 0 L L L l l H H H H H H H H L L L H H L H H H H H H H H I l I H L H H l H H H H H H H 3 L L H H H H H L H H H H H H 4 l H L L H H H H L H H H H H L H L H H H H H H l H H H H L H H L H H H H H H l H H H l H H H H H H H H H H L H H H L I I M H H H H H H H L H H L L H H H H H H H H H H l tot L H L H H H H H H H H H H i ...

Page 103: ...h impedance state while the other input passes the data through the buffers The outputs are placed in the tri state condition by applying a high logic level to the control pins Logic and connections are shown in Figure 4 19 Logic and Connection Diagram Truth Table 1 I u o INPUTS OUTPUT G A Y H X H Z l H H L l L III AI VI 42 2 43 VJ GNO Figure 4 19 Tri State Buffer Connections 4 69 ...

Page 104: ...o the output occurs when the STROBE input goes from a logical 1 to a logical 0 state Inputs may be changed while the STROBE is at the logical 1 level without affecting the state of the output Logic and connections are shown in Figure 4 20 T 14 lllIIl fI 141 Illl A H _ 11 111 _ Logic Diagram Figure 4 20 Connection Diagram II I 114 14 Out UT lI II It U II It II t I j J 4 r I fI U U 13 tl ftlHllf Cil...

Page 105: ...his device provides six two input buffers in each package One of the two inputs is used as a control line to gate the output into a high impedance state while the other passes the data through the buffer The outputs are placed in the tri state condition by applying a high logic level to the control pins See Figure 4 22 for logic diagram and truth tab Ie Logic Diagram Truth Table U t VI A INPUTS OU...

Page 106: ...ng a high logic level to the enable pins See Figure 4 23 for logic diagram and truth table Logic and Connection Diagram Truth Table INPUTS OUTPUT G A V H X Z L H l l L H 1 1 AI Vi A1 l AJ l A4 1 4 IlND Figure 4 23 Tri State Buffer Connections 4 2 10 DUAL J K NEGATIVE EDGE TRIGGERED FLIP FLOPS WITH PRESET UB See Figure 4 24 for logic diagram and truth table Connection Diagram elI IU I AI If Truth T...

Page 107: ... l r x L L H 1 u U t 1 Co N I L OM l1li 1_1 pul Lr OM I pul To u Ifte neI limine or of 21 2 OlIn RINT to ce An ell nal limine Ior I WWV be connected n CfXT end EXT CEXT DOIiliVilI For eccurate repM pu wldtft CD aft e l rl lll r littor between RE T CEXT And ec with INT ope lircUl IICI To obuin ie put width CORI Iet neI Wllimi _ berw R NT or REX TiCE T ItICI Vee Figure 4 25 One Shot Connections 4 73...

Page 108: ... tab Ie Connection and Logic Diagram JII U I t 1 UTA OUTPUll VI II II eJA on 1loIll 4 1 II t po I JI 81 Yl UD BU 1 II1 Truth Tab Ie INPUTS OUTPUTS ENABLE SELECT 01 02 e 8 A f0 Y1 Y2 Y3 Y4 H X X X H H H H H L X X X H H H H H H L L L L L H H H H H l l I H H L H H H H L l H l H H l II H H l L H H H H I It H L H l l H H H H l H l H l H H H H H H H l H H L H H H H H H l H H H H H H H H Q2 G2A 028 M H L...

Page 109: ...utput high and the Y output low For logic and truth table see Figure 4 27 lATA 1M A e f II n II II II I I a tt I I I It n M n J INfIUTI 0IJ11IUI I _LICT ITROM y W C A II H L H l l L L DO is L L H L D1 lfi L H L L D2 i2 L H H L D3 13 H L L L DI Ii H L H L DI iii H H L L De Iii H H H L D1 II H H_ If L Low Mel X CDn c r Ii ri Iii I of of II OCt 01 01 0 t AMUIlauf MUL E rflfll t Figure 4 27 Data Selec...

Page 110: ...High Impeal ce btl Iale OUTPUTS va Yb H H L L Z Z Figure 4 28 Tri State Inverter Buffer Connections 4 2 15 TRI STATE OCTAL BUFFER U41 This device is a non inverting octal buffer r interface between tri state busses See Figure 4 29 for connections and truth table Pin Configuration Truth Table Figure A Figure 4 29 INPUTS OEa la I OEb L L I L L H I L H X I H H HIGH lIolla e he L bLOW vOlta f hel 001 ...

Page 111: ...t gated master reset clear See Figure 4 30 for logic diagram and truth table Pm numl flrs IICC Pin 01 GND PIn 7 Logic Diagram Pin Configuration Truth Table Mode Selection OUTPUT COUNT 00 0 02 03 0 L L L L RESET OUTPUTS INPUTS 1 H L L L MR MR2 00 0 02 03 2 L H L L 3 H H L L H H l L L L L H Count 4 L L H L H L Count 5 H L H L L L Count 6 L H H L 7 H H H L H 110H nllage t v 8 L L L H 9 H L L H L lOW ...

Page 112: ...he voltage sensitive inputs one for frequency control and the other for frequency range These inputs can be used to vary the output frequency by changing the voltage applied to them An enable input provides control of the device output A low enable input enables the output and a high enable produces a high output for Y and a low for Y See Figure 4 31 for device connections 1000e _ deotCl iption Fi...

Page 113: ...the high impedance state When a low logic level is applied to the output control data at the D inputs are loaded into their respective flip flops on the next positive going transition of the clock See Figure 4 32 for logic diagram and truth table Connection Diagram IIcc III III 111 Q1 D I 01 Ql CLI t OUTPUT 01 CDlIIllUH Truth Table OUTPUT CLOCK D OUTPlh CONTROL L t H H L t L L l L 00 H z Logic Dia...

Page 114: ...is available See Figure 4 33 for logic diagram and truth table Connection Diagram TOP ViEW OUTPU TS _ _ J _ _ OUTPUTS PQliliV8 logic H gh nput to clear relets all four outputs low Truth Table COUNT SEOUENCE lEACH COUNTER COUNT OUTPUT aD Oc aB aA 0 L I L L t L L L H 2 L L H L 3 L L H H 4 L H L L 6 L H L H 6 L H H 1 7 L H H H 8 H L L L 9 H L L H 10 H L H L l H L H H 12 H H L L 13 H H L H 14 H H H L ...

Page 115: ...e provided at 20 increments of total delay The device accepts either a logic one or zero inputs and reproduces the logic at the selected output tap without inversion Block diagram and connections are shown in Figure 4 34 Block Diagram r f I I I I I I L_ INfIOT ow to OUTIl UT I t I I I I _ J lOtI QAOUNO Connections Figure 4 34 Logic Delay Module Diagram and Connections 4 81 ...

Page 116: ...select input enables all of the out puts An inactive level at the chip select input causes all outputs to be off Capacity is 256 bits or 32 words by 8 bits Connections and I O circuits are shown in Figure 4 35 DO 1 18 Vee EOUIVALENT OF TVPICAlOF EACH INPUT AllOUTPUIS DO 2 2 15 S vcc DO 3 3 AD E vcc DO 13 AD 0 DO 6 6 12 AD e INPUT OUT I JT 008 6 11 AD B DO 1 1 10 AD A GND 8 9 DO 8 PrOG ammlnG tlreu...

Page 117: ... positive going e of the clock pulse Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive going pulse When the clock input is at either the high or low level the D input signal has no effect at the output For logic and connections see Figure 4 36 Logic Diagram Figure 4 36 Connections Truth Table FUNCTION TAaLE lEACH FLIfO FLMI INP...

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Page 119: ...ions Two and Three of this manual are met Should a problem arise after the circuit card has been in operation use the following procedures to identify and locate the fault 1 Check all cabling for proper seating of connectors 2 Check the circuit board for proper seating in the slot 3 Check all power connections for correct voltages 4 Check jumper options to ensure correctness of application 5 Verif...

Page 120: ...AM 210 Floppy Disk Controller circuit board When this diagnostic is successfully performed with a disk drive that is known to be good all aspects of the AM 210 cir cuit board can be qualified as operational Diagnostic opera ting procedures and a description of the tests are contained in the following paragraphs 5 3 1 OPERATIONAL TEST The following procedure can be performed as an overall opera tio...

Page 121: ...py interface drive test E EVAL Final system evaluation procedures To begin this diagnostic locate the major portion of the diagnostic called AM 2ID RUN LOG into that particular PPN and type the following RUN AM2lD To do this correctly you will have to verify that the SYSTEM INI file allows for loading into system memory BASIC PRG and RUN PRG Accomplish this by using VUE and altering the SYSTEM INI...

Page 122: ... 5 lK On Board RAM 6 RAM Address Coun ter This routine writes three different data patterns to the on board RA Each pattern is read back and checked for errors If any occur the actual data will be listed as well as the RAM location and the expected pattern The three patterns written are 0 85 170 DECIMAL Note that in binary code these patterns are as shown below o 170 85 000 0 0 0 0 0 101 0 1 010 o...

Page 123: ... this point the data pattern returns to zero A binary represen tation of the pattern will clarify its correlation to the unique RAM address A9 A8 A7 A6 AS A4 A3 A2 Al AO 512 256 128 64 32 16 8 4 2 1 0 0 0 0 0 0 0 0 ADDR 1 0 0 0 0 0 0 0 0 ADDR 1 0 0 0 0 0 0 0 0 0 ADDR 0 256 512 In all three cases the address lines AO A7 are all O Because the data bus is only 8 lines wide the maximum number is 28 or...

Page 124: ...nal operations For a pattern read the printout reads the foll wing TRACK DATA PATTERN OF 15 NO ERRORS SECTOR DATA PATTERN OF 15 NO ERRORS DREQ DATA PATTERN OF 15 NO ERRORS PASS 15 COMPLETE If an error occurs th printout appears as TRACK WAS 255 EXPECTED 15 SECTOR DATA PATTERN OF 15 NO ERRORS DREQ DATA PATTERN OF 15 NO ERRORS PASS 15 COMPLETE The total errors accumulated at the end of the test for ...

Page 125: ...und and U10 14 for 5 volts 5 3 2 3 FLOPPY DRIVE SEEK TEST AND DATA SEPARATOR CALIBRATION SEEK This routine used as an aid to checking and calibrating the data clock separator circuit This test checks all of the following system blocks 1 FDC chip partial check on floppy drive interface lines 2 External control register No 1 partial check on drive select signals and double density state signal 3 Ext...

Page 126: ...ette be used for calibration pur poses Select the restore function and verify that the selected drive is at TRACK O This should be tested in the following three ways 1 Physically inspect the drive s ected and note that the head mechanism is positioned at TRACK 0 outer most portion of the floppy diskette 2 Scope Ul 34 and verify that it is low 3 Read the information indicated on the CRT screen and ...

Page 127: ...SCI or a mini floppy since the step rates involved are not capable of being selected Connect a scope probe of channel one to the pad labeled RCLK near Ul This can also be connected via U12 pin S This pulse period should be approximately 4 usec The pulse width is approximately 2 usee Use channel 1 as the trigger source and sync the scope on the normal mode with this signal Take the channel two prob...

Page 128: ... time is now halved each pulse width is 1 uSee in duration for a 2 uSec pulse per iod The Head Load O S should also be checked for proper timing Connect channel one to U14 12 and set for a negative going pulse duration for 5 mSec per division Each time the drive is initially selected and the head is to be loaded this output should go low for approximately 40 mSec This is defined for 01 02 04 05 re...

Page 129: ...for using both For physical drive numbers and actual numbers a list is illustrated below DRIVE o 1 2 3 a 1 2 3 WANGCO SHUGART 0000 1 0001 0001 2 0010 0010 4 0100 0011 8 1000 The step routine for dual drives 3 can be selected for as many passes as desired At the end of the passes the total number of errors for each drive are totalled and listed This is essenti ly done by checking each step position...

Page 130: ...ve The command list for this portion of the qiagnostic appears as the following SET VALUES SEEK ONLY GET STATUS RESTORE READ SBCTOR PRINT ON BOARD RAM FILL RAM WRr SECTOR RETURN TO MAIN MENU These commands allow for speci c functions to occur to from the AM 210 and the floppy drive After each function has been completed the diagnostic returns once again to this command list to begin the next desir...

Page 131: ...ually set for 6 Double Density Mode Y N For double density diskettes type a nyu for yes Standard dis kettes type an UN for no Load ads Y N This selects whether the heads are to be loaded during the seek operations To verify the position via the track address mark on the diskette select yes Most cases should always select a Yes for this routine AM 210 Board Number 0 1 2 1 Normal operation selects b...

Page 132: ... number can be any number from 0 to 76 The CRT next asks for the sector number The user may select from 1 to 26 The system then seeks to this desired position and verifies the correct location by checking the address mark on the diskette A statu is printed out on the screen A 32 status is no errors a status of 48 is typically an error Note that a seek routine as well as a restore are both con side...

Page 133: ...and is chosen as the first 128 bytes of on board RAM The system prints out the actual location and the status of the Write command Note that the data pattern indicated illustrates the last data pattern selected to be written into the on board RAM Thus this register is not updated until another data pattern is chosen for RAM A status of 0 indicates no errors The actual meaning for each status bit i...

Page 134: ...l RAM with 200 from a to 200 The entire purpose behind the on board RAM is storage of data records to from the 5 3 2 5 EVALUATION PROCEDURE r temporary oppy drive In order to finalize all aspects of the AM 2ID it is necessary to perform system command routines which exercise all portions of the AM 2ID In addition this procedure is the ONLY method to easily investigate the following system blocks f...

Page 135: ...al and the Write Track command See section 3 4 for diskette formatting The boot routine logic is easily tested by installing the necessary boot PROM and jumpering the AM 210 for the BOOT ROUTINE It is recommended that a known good PROM be used to test the rest of the circuitry 5 17 ...

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Page 137: ... 2 0 1 2 2J t J2 J L J33 l 2 12 Uo LDM500 4 2 20 U30 211 4 2 2 U8 7 1 LSl13 l 2 10 UJl 2114 i 2 2 U9 LS393 4 2 19 lJ33 L02 1j 0 2 l1f U12 16 LS7 1 It 2 7 U34 LS2 j 4 2 22 J 13 7445 4 2 4 UJS LJ273 4 2 22 U11 26LS123 4 2 11 036 81L s 1 4 2 8 U16 8097 4 2 5 U39 81LS93 4 2 9 U17 1S 1 4 2 13 U40 L3240 U1 J 2GLS123 4 2 11 U41 L321 4 4 2 15 U19 LS28G 1 2 2 1 U43 LS374 4 2 18 U20 LS393 1 2 19 U21 2708 4 ...

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Page 139: ...7 I C 1 4 3 if l PCf t DOUBLE DEN ITY FLOPPY AH l O ASf f 0 H A 1 2 1 1 C DUAL 4 BIT BIN AF yeoUNTF P Ie DOUBLE DENSITY FLOPPY DI t CONT 1 f DEL FTED PAF T c C B I PUT MUL r I F tL EXEf Ie 4 BIT BINARY COUNTER Ie BCD DECIM L DECODEF I C VOL Tf GE CONTf OI I ED O C I LL TDf f F N 1ST DF P NP TF N 3 J GT0H NPN F Er J ST0 F TRJ M PDT 1 UL TIT Uf N 1 01 leo elL L AT f l C MH7 Ie AMPLIFIER OPERATIONAL ...

Page 140: ...11 f _ I B 8V 10 ICI4 lefs lc sv2 Gt J1 IOOr tr 4 _ __ l D_1_ o l 0 _____ TD 1_ l O_ __ A 1 1 4 3 2 l l U32 U3e U3B BILSS7 LS2 l 1 LS it 1f V 2112 18 9 41 l 1tl b 8 12 U27 U42 LS32 S Il LS240 J3 8 12 II 1 9 TABULATION BLOCK DASH DESCRIPTIOt aipha micro J _ t j T r Tt a n ...

Page 141: ..._ l 6 13 II IOAI2 13 9 r H f Jr 12 11 15 AIO 7 2A125 __ 3 __________ L_ l A6 WR 1 PRESET 75 4 3 FO f 2 5 S P 3 U23 15 AI 2 i4 f O J_ r _ FI IC l Of l t l A I 2 I __ A IJISIOMS P l OF1T 18 U40 2 DA 7 i i 4 I I I D LG __ I I i dcha i rTlIcro ...

Page 142: ...D c B A 4 3 2 H7 J IB Tt C LeAD PRDY CO _ EN 5 E 2 P LY L0G t REA 4 3 XTE2 STAT D TA I Rffh r u _ I l I t S hfo _ Iooll I Hl t n i ____ L________ ______ _____ 2 R YISlOtlS jalpha r micro ...

Page 143: ...3 R5TAR 4 l l lS240 U9 3 I 5 lS 6 393 4 8MHl 4 Z 2 Kl l eLK SH4 6 C OI MOD 02 MOD 3 5 6 7 3 17 16 15 FO 9 _ MOO U9 6 TO Cl 2 CUT ETCH 1 9 5 TO eLK 3 8 5 U3I 2114 io w 12 3 14 9 i 2 T D 4 L 0 alpha z f micro Du l DE SIT FI_ Y S CG 2T4 L K tr coco _ ...

Page 144: ... I JI PRDY H3 B02 CLK SV II 2S 10 741b 9 C R28 470n BDRQr E J 81NTR 10 IlJ Q r 741f 6 5V ClO R24 330PF 10K 7416 14 1 0 5 f 13 _ c13 l28 2 Ufo 700NS C 4 iro 0 5 I i I I 0 6 2 SIi3 L08DSEL 1 0 7 3 2 4 sit 3 I 5 i SIVT LSI23 41 STR Hsl 5r e TR INTR 10 i 6 0 II vT7 alpha I I r 7 1 r r S EIiI _I I O s IiI s OUIU IS I r 1 S lES lTucrc __ i D J QE r ITT C LGI Y r _j C O I TP 0 I C I i I O Cl SC A l _n _ ...

Page 145: ... J IiA L Ji t 1 1 i lli y o r 7f A C l 6 o c B A 4 I I 13 3K I I I I I I I I L I OP E ICH J Fon 4 3 1 5 __ F1C L K Sri6 6 1 l 3 t 2 _ l 5 I COPP j TCH I j I I I I I I ...

Page 146: ...c t SH3 vD WDAO Wt A1 DAL7 I 6 5 4 3 2 I DALO r l M f UI 2 3 2 5 37 33 29 TG l3 14 16 DIR 13 12 27 26 RCL 25 RG I f vC y oILD 2B FDI791 2J HIT 15 STEP RI7 150n BOOur I DELAy TIMES DOUBLE FOR OS REV ONLY n i j 3 2 J3 U33 14 G ih A A c 36 STIP 20 f ...

Page 147: ...oSEL MHZ r I I AD A9 BOOT CLOCK I PROM U9 UlO 021 2MHZ BRO afNTR FLOPPY CONTROLLER MODULE Ul aom A1 A2 11 B gIT RAMI CONTROL U9 U20 UJO U31 iiAMCS W i5WE ORa PROCESSOR U8 U19 U43 WRTFLOPPY FORMAT aOOUTO 7 toeR 1 LOCR PHANTOM 1 I i 8i Se iiDAE PSTR PROY v CONTROL LOGIC BINTR BORO US U18 U27 R v O VI7 o 10 WOo WRITE LATe EARLY PRECQMPEN SATION U6 U16 U17 RCLK OATA CLOCK DO SEPARATOR 1 I ilEP EXTERNA...

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Page 149: ...HEAT SINK 7S0WI 375HT 750LG SCREW 6 32 X 250 NUT HEX 6 32 STl SH F ATTEF N WASHER LOCK 6 32 SCREW 6 32 X 750 NYL NUT HEX 6 32 NYL 8M PATTERN MICA PAD TO 220 HEADER 50 PIN W O EJC RT ANGLE HEADER 26 PIN W O EJC RT ANGLE CAPACITOR 47 PF CAPACITOR 100 PF CAPACITOR 1000 PF CAPACITOR 01 UF CAPACITOR 33 UF SOU DIODE SIGNAL IN4148 RESISTOR 1 K 1 4W 5 CAR RESISTOR 10 K 1 4H 5 CAR RESISTOR 150 OHM 1 4W 5 C...

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