Chapter 3
DDR SDRAM Interface
161
24081D—February 2002
AMD-761™ System Controller Software/BIOS Design Guide
Preliminary Information
Example configurations are shown in Table 26.
3.5
Additional Memory Controller Settings
This section discusses configuration features that are specific
to the AMD-761 system controller DDR memory controller. The
AMD-761 memory controller contains DDR memory controller
settings starting at (Dev 0:F0:0x54). These settings are Page
Hit Limit, Idle Cycle Limit, Registered DIMM Enable device
control (used in this register to specify registered versus
unbuffered DIMM), Read Wait State timing control, selectable
H O L D t i m e fo r t he D D R a dd re s s a nd c o m m a n d b us e s
(selectable per address and command bus A and B), and a
selectable wait state for Super Bypass control.
Page Hit Limit
The Page Hit Limit bits (Dev 0:F0:0x54, bits [15:14]) specify
the number of conse cutive Pa ge Hit requests that are
processed by the AMD-761 DRAM controller before choosing a
non-page hit request. This feature is designed to reduce
starvation (a pending request not fulfilled for an extended
period of time) due to a flood of consecutive page hit requests.
Typically, consecutive page hits yield the best DDR DRAM
page performance for those requesting devices (such as the
CPU or PCI device, etc.). However, starvation of a request
because it is a non-page-hit request does not constitute a fair
system memory access policy.
When the number of consecutive page hits across
all
internal
DDR device internal banks of a given chip select equals the
value specified in these bits, the DDR controller arbiter gives
priority to a DDR memory request that is
not
a page hit. It was
determined that eight consecutive page hit accesses is
Table 26.
Dev 0:F0:0x54 Bit Examples
CL
DIMM
Dev 0:F0:0x54
57 56 55 54
2
100 MHz Unbuffered
16 01 88 B5
2
100 MHz Registered
7E 01 88 B5
2.5
133 MHz Unbuffered
96 01 8C 4A
2.5
133 MHz Registered
F6 01 8E 5A
