ADVANCED CHIPSET SETUP Options,
Continued
On Board Parallel Port
This option enables or disables the onboard parallel port. The settings are I/O port address
378h
-37Fh,
278h
-27Fh, or
Disabled
. P5 is the onboard parallel port. If the configuration data stored in CMOS RAM is corrupted when the system is
powered on, AMIBIOS automatically configures the onboard parallel port according to the presence or absence of parallel
ports on adapter cards in the expansion slots (offboard parallel ports). Autoconfiguration only occurs when CMOS RAM data is
corrupted. The result for the onboard parallel port is:
If the Offboard
Parallel Port is
the Onboard Parallel Port is Autoconfigured as
None or 3BCh
378h
Can be disabled or changed to 278h via ADVANCED
CHIPSET SETUP.
378h
278h
Can be disabled via ADVANCED CHIPSET SETUP. If
changed to 378h, an I/O port address conflict occurs.
278h
378h
Can be disabled via ADVANCED CHIPSET SETUP. If
changed to 278h, an I/O port address conflict occurs.
378h, 278h
Disabled
If changed to 378h or 278h, an I/O port address
conflict occurs.
P5 is the parallel port on the Mark V motherboard. If disabled through Setup, do not attach any device to P5 or to any cable
attached to P5. J23 is used to configure the interrupt request line (IRQ) for the onboard parallel Port. The J23 settings are:
Jumper
Pins Shorted
Description
J23
Pins 1-2
IRQ5 selected for the onboard parallel port.
J23
Pins 2-3
IRQ7 selected for the onboard parallel port (Default).
If the onboard parallel port is disabled, you can remove the jumper block from J23 to disable the onboard parallel port
interrupt.
Summary of Contents for 42 Series
Page 1: ...American Megatrends Inc Series 42 Mark V Baby Screamer 80386 Motherboard User s Guide ...
Page 2: ...MAN 642 Rev C 9 11 92 ...
Page 13: ......
Page 35: ...A29 SA02 B29 5 A30 SA01 B30 OSC A31 SA00 B31 GND ...
Page 59: ......
Page 82: ......
Page 85: ...SRAM Locations ...