Chapter Three : AMIBIOS Setup
109
Section 6 Chipset Setup,
Continued
NorthBridge Chipset Configuration
NorthBridge Chipset Configuration
v02.53 (C) Copyright 1985-2003, American Megatrends, Inc.
Main
Advanced
PCIPnP
Security
Exit
Power
Boot
Chipset
Select Screen
Select Item
Change Option
General Help
Save and Exit
Exit
+ -
F1
F10
ESC
Frequency of DRAM
DRAM Frequency
Configure DRAM Timing by SPD
DRAM Integrity Mode
Memory Hole
Primary Graphics Adapter
Graphics Aperture Size
C.S.A Gigabit Ethernet
Onboard VGA Configuration :
[Auto]
[Enabled]
[Disabled]
[Disabled]
[AGP]
[ 64MB]
[Auto]
[Enabled]
DRAM Frequency
The value represents the performance parameters of the installed memory chips (DRAM).
Do not change the value from the factory setting unless you install new memory that has
a different performance rating.
Option Description
266 MHz
This value changes the DRAM frequency to 266 MHz.
333 MHz
This value changes the DRAM frequency to 333 MHz.
400 MHz
This value changes the DRAM frequency to 400 MHz.
Auto
This value allows the BIOS to auto detect the DRAM frequency. This is
the default value.
Configure DRAM Timing by SPD
SPD (Serial Presence Detect) is located on the memory module. The BIOS can read
information coded in SPD during system boot up.
Option Description
Disabled
This value prevents the SDRAM Timing to be set by the SPD.
Enabled
This value allows the SDRAM Timing to be set by the SPD. This is the
default value.
Cont’d
Summary of Contents for Olympus III
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Page 14: ...American Megatrends Inc Olympus III User s Guide Series 875 4 Rear I O Ports...
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