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REV. 0

AD1887

–14–

Serial Configuration (Index 74h)

g

e

R g

e

R g

e

R g

e

R g

e

R

m

u

N m

u

N m

u

N m

u

N m

u

N

e

m

a

N

e

m

a

N

e

m

a

N

e

m

a

N

e

m

a

N

5

1

D 5

1

D 5

1

D 5

1

D 5

1

D

4

1

D 4

1

D 4

1

D 4

1

D 4

1

D

3

1

D 3

1

D 3

1

D 3

1

D 3

1

D

2

1

D 2

1

D 2

1

D 2

1

D 2

1

D

1

1

D 1

1

D 1

1

D 1

1

D 1

1

D

0

1

D 0

1

D 0

1

D 0

1

D 0

1

D

9

D9

D9

D9

D9

D

8

D8

D8

D8

D8

D

7

D7

D7

D7

D7

D

6

D6

D6

D6

D6

D

5

D5

D5

D5

D5

D

4

D4

D4

D4

D4

D

3

D3

D3

D3

D3

D

2

D2

D2

D2

D2

D

1

D1

D1

D1

D1

D

0

D0

D0

D0

D0

D

t

l

u

a

f

e

D

t

l

u

a

f

e

D

t

l

u

a

f

e

D

t

l

u

a

f

e

D

t

l

u

a

f

e

D

h

4

7 h

4

7 h

4

7 h

4

7 h

4

7

l

a

i

r

e

S

l

a

i

r

e

S

l

a

i

r

e

S

l

a

i

r

e

S

l

a

i

r

e

S

n

o

i

t

a

r

u

g

i

f

n

o

C

n

o

i

t

a

r

u

g

i

f

n

o

C

n

o

i

t

a

r

u

g

i

f

n

o

C

n

o

i

t

a

r

u

g

i

f

n

o

C

n

o

i

t

a

r

u

g

i

f

n

o

C

6

1

T

O

L

S

6

1

T

O

L

S

6

1

T

O

L

S

6

1

T

O

L

S

6

1

T

O

L

S

2

M

G

E

R

2

M

G

E

R

2

M

G

E

R

2

M

G

E

R

2

M

G

E

R

1

M

G

E

R

1

M

G

E

R

1

M

G

E

R

1

M

G

E

R

1

M

G

E

R

0

M

G

E

R

0

M

G

E

R

0

M

G

E

R

0

M

G

E

R

0

M

G

E

R

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

h

0

0

0

7

h

0

0

0

7

h

0

0

0

7

h

0

0

0

7

h

0

0

0

7

Note: This register is not reset when the reset register (Register 00h) is written.

DHWR

Disable Hardware Reset.

REGM0

Master Codec Register Mask.

REGM1

Slave 1 Codec Register Mask.

REGM2

Slave 2 Codec Register Mask.

SLOT16

Enable 16-bit slots.

If your system uses only a single AD1887, you can ignore the register mask bits.

SLOT16 makes all AC Link slots 16 bits in length, formatted into 16 slots.

Miscellaneous Control Bits (Index 76h)

g

e

R g

e

R g

e

R g

e

R g

e

R

m

u

N m

u

N m

u

N m

u

N m

u

N

e

m

a

N

e

m

a

N

e

m

a

N

e

m

a

N

e

m

a

N

5

1

D 5

1

D 5

1

D 5

1

D 5

1

D

4

1

D 4

1

D 4

1

D 4

1

D 4

1

D

3

1

D 3

1

D 3

1

D 3

1

D 3

1

D

2

1

D 2

1

D 2

1

D 2

1

D 2

1

D

1

1

D 1

1

D 1

1

D 1

1

D 1

1

D

0

1

D 0

1

D 0

1

D 0

1

D 0

1

D

9

D9

D9

D9

D9

D

8

D8

D8

D8

D8

D

7

D7

D7

D7

D7

D

6

D6

D6

D6

D6

D

5

D5

D5

D5

D5

D

4

D4

D4

D4

D4

D

3

D3

D3

D3

D3

D

2

D2

D2

D2

D2

D

1

D1

D1

D1

D1

D

0

D0

D0

D0

D0

D

t

l

u

a

f

e

D

t

l

u

a

f

e

D

t

l

u

a

f

e

D

t

l

u

a

f

e

D

t

l

u

a

f

e

D

h

6

7 h

6

7 h

6

7 h

6

7 h

6

7

c

s

i

M c

s

i

M c

s

i

M c

s

i

M c

s

i

M

l

o

r

t

n

o

C

l

o

r

t

n

o

C

l

o

r

t

n

o

C

l

o

r

t

n

o

C

l

o

r

t

n

o

C

s

t

i

B s

t

i

B s

t

i

B s

t

i

B s

t

i

B

Z

C

A

D

Z

C

A

D

Z

C

A

D

Z

C

A

D

Z

C

A

D

X

I

M

P

L

X

I

M

P

L

X

I

M

P

L

X

I

M

P

L

X

I

M

P

L

X

X

X

X

X

M

A

D M

A

D M

A

D M

A

D M

A

D

S

M

D

S

M

D

S

M

D

S

M

D

S

M

D

R

S

L

D

R

S

L

D

R

S

L

D

R

S

L

D

R

S

L

D

X

X

X

X

X

R

S

L

A

R

S

L

A

R

S

L

A

R

S

L

A

R

S

L

A

D

O

M D

O

M D

O

M D

O

M

D

O

M

N

EN

EN

EN

EN

E

0

1

X

R

S

0

1

X

R

S

0

1

X

R

S

0

1

X

R

S

0

1

X

R

S

7

D7

D7

D7

D7

D

8

X

R

S

8

X

R

S

8

X

R

S

8

X

R

S

8

X

R

S

7

D7

D7

D7

D7

D

X

X

X

X

X

X

X

X

X

X

R

S

R

D

R

S

R

D

R

S

R

D

R

S

R

D

R

S

R

D

X

X

X

X

X

R

S

R

A

R

S

R

A

R

S

R

A

R

S

R

A

R

S

R

A

h

4

0

4

0

h

4

0

4

0

h

4

0

4

0

h

4

0

4

0

h

4

0

4

0

ARSR

ADC Right Sample Generator Select
0 = SR0 Selected (32h)
1 = SR1 Selected (2Ch)

DRSR

DAC Right Sample Generator Select
0 = SR0 Selected (32h)
1 = SR1 Selected (2Ch)

SRX8D7

Multiply SR1 rate by 8/7.

SRX10D7

Multiply SR1 rate by 10/7. SRX10D7 and SRX8D7 are mutually exclusive; SRX10D7 has priority if both are set.

MODEN

Modem filter enable (left channel only). Change only when DACs are powered down.

ALSR

ADC Left Sample Generator Select
0 = SR0 Selected (32h)
1 = SR1 Selected (2Ch)

DLSR

DAC Left Sample Generator Select
0 = SR0 Selected (32h)
1 = SR1 Selected (2Ch)

DMS

Digital Mono Select
0 = Mixer
1 = Left DAC + Right DAC

DAM

Digital Audio Mode. DAC Outputs bypass analog mixer and sent directly to the codec output.

LPMIX

Low-Power Mixer

DACZ

Zero-fill (vs. repeat) if DAC is starved for data.

Summary of Contents for AD1887

Page 1: ... Bit Headphone Volume Control Digital Audio Mixer Mode AC 97 2 1 FEATURES Variable Sample Rate Audio AC 97 FEATURES AC 97 2 2 Compliant Greater than 90 dB Dynamic Range Integrated Stereo Headphone Amplifier Multibit Converter Architecture for Improved S N Ratio Greater than 90 dB 16 Bit Stereo Full Duplex Codec Two Analog Line Level Stereo Inputs for LINE IN and CD Mono MIC Input with Built In Pro...

Page 2: ...to HP_OUT 90 dB Other to HP_OUT 90 dB Step Size 12 dB to 34 5 dB All Steps Tested MIC LINE_IN CD DAC 1 5 dB Input Gain Attenuation Range MIC LINE_IN CD DAC 46 5 dB DIGITAL DECIMATION AND INTERPOLATION FILTERS Parameter Min Typ Max Unit Pass Band 0 0 4 fS Hz Pass Band Ripple 0 09 dB Transition Band 0 4 fS 0 6 fS Hz Stop Band 0 6 fS Hz Stop Band Rejection 74 dB Group Delay 12 fS sec Group Delay Vari...

Page 3: ...UT Input R Zero L 80 dB Measure L_OUT Total Audible Out of Band Energy Measured from 0 6 fS to 20 kHz 40 dB ANALOG OUTPUT Parameter Min Typ Max Unit Full Scale Output Voltage HP_OUT 1 V rms 2 83 V p p Output Impedance 800 Ω External Load Impedance 32 Ω Output Capacitance 15 pF External Load Capacitance 100 pF VREF 2 05 2 25 2 45 V VREF_OUT 2 25 V VREF_OUT Current Drive 5 mA Mute Click Muted Output...

Page 4: ...idth tSYNC_HIGH 1 3 µs SYNC Low Pulsewidth tSYNC_LOW 19 5 µs SYNC Inactive to BIT_CLK Startup Delay tSYNC2CLK 162 8 ns BIT_CLK Frequency 12 288 MHz BIT_CLK Period tCLK_PERIOD 81 4 ns BIT_CLK Output Jitter 750 ps BIT_CLK High Pulsewidth tCLK_HIGH 32 56 42 48 84 ns BIT_CLK Low Pulsewidth tCLK_LOW 32 56 38 48 84 ns SYNC Frequency 48 0 kHz SYNC Period tSYNC_PERIOD 20 8 µs Setup to Falling Edge of BIT_...

Page 5: ...SYNC tHOLD SDATA_OUT tSETUP Figure 4 Data Setup and Hold BIT_CLK SYNC SDATA_IN tRISECLK tRISESYNC tRISEDIN tRISEDOUT tFALLCLK tFALLSYNC tFALLDIN tFALLDOUT SDATA_OUT Figure 5 Signal Rise and Fall Time BIT_CLK SDATA_OUT SYNC SDATA_IN SLOT 1 SLOT 2 WRITE TO 0x26 DATA PR4 DON T CARE tS2_PDOWN NOTE BIT_CLK NOTTO SCALE Figure 6 AC Link Low Power Mode Timing RESET SDATA_OUT HI Z tSETUP2RST tOFF SDATA_IN ...

Page 6: ...al operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ORDERING GUIDE Temperature Package Package Model Range Description Option AD1887JST 0 C to 70 C Thin Quad Flatpack ST 48 ENVIRONMENTAL CONDITIONS Ambient Te...

Page 7: ...ferential CD Input CD_ R 20 I CD Audio Right Channel MIC 21 I Microphone Input LINE_IN_L 23 I Line in Left Channel LINE_IN_R 24 I Line in Right Channel HP_OUT_L 39 O Headphones Out Left Channel HP_OUT_R 41 O Headphones Out Right Channel Filter Reference These signals are connected to resistors capacitors or specific voltages Pin Name TQFP I O Description VREF 27 O Voltage Reference Filter VREFOUT ...

Page 8: ... X X X RS2 RS1 RS0 0000h 1Ch Record Gain IM X X X LIM3 LIM2 LIM1 LIM0 X X X X RIM3 RIM2 RIM1 RIM0 8000h 20h General Purpose X X X X X X X X LPBK X X X X X X X 0000h 26h Power Down Ctrl Stat X X PR5 PR4 PR3 PR2 PR1 PR0 X X X X REF ANL DAC ADC 000Xh 28h Ext d Audio ID ID1 ID0 X X X X X X X X X X X X X VRA 0005h 2Ah Ext d Audio Stat Ctrl X X X X X X X X X X X X X X X VRA 0000h 2Ch PCM DAC Rate SR1 SR...

Page 9: ...The AD1887 contains none of the optional features identified by these bits SE 4 0 Stereo Enhancement The 3D stereo enhancement identifies the Analog Devices 3D stereo enhancement Headphones Volume Registers Index 04h g e R g e R g e R g e R g e R m u N m u N m u N m u N m u N e m a N e m a N e m a N e m a N e m a N 5 1 D 5 1 D 5 1 D 5 1 D 5 1 D 4 1 D 4 1 D 4 1 D 4 1 D 4 1 D 3 1 D 3 1 D 3 1 D 3 1 D...

Page 10: ... L 1 V L L 1 V L L 1 V L L 1 V L L 1 V L L 0 V L L 0 V L L 0 V L L 0 V L L 0 V L L X X X X X X X X X X X X X X X 4 V L R 4 V L R 4 V L R 4 V L R 4 V L R 3 V L R 3 V L R 3 V L R 3 V L R 3 V L R 2 V L R 2 V L R 2 V L R 2 V L R 2 V L R 1 V L R 1 V L R 1 V L R 1 V L R 1 V L R 0 V L R 0 V L R 0 V L R 0 V L R 0 V L R h 8 0 8 8 h 8 0 8 8 h 8 0 8 8 h 8 0 8 8 h 8 0 8 8 RLV 4 0 Right Line In Volume Allows s...

Page 11: ...D3 D3 D 2 D2 D2 D2 D2 D 1 D1 D1 D1 D1 D 0 D0 D0 D0 D0 D t l u a f e D t l u a f e D t l u a f e D t l u a f e D t l u a f e D h A 1 h A 1 h A 1 h A 1 h A 1 t c e l e S d r o c e R t c e l e S d r o c e R t c e l e S d r o c e R t c e l e S d r o c e R t c e l e S d r o c e R X X X X X X X X X X X X X X X X X X X X X X X X X 2 S L 2 S L 2 S L 2 S L 2 S L 1 S L 1 S L 1 S L 1 S L 1 S L 0 S L 0 S L 0 ...

Page 12: ... n w o D r e w o P X X X X X 6 R P 6 R P 6 R P 6 R P 6 R P 5 R P 5 R P 5 R P 5 R P 5 R P 4 R P 4 R P 4 R P 4 R P 4 R P 3 R P 3 R P 3 R P 3 R P 3 R P 2 R P 2 R P 2 R P 2 R P 2 R P 1 R P 1 R P 1 R P 1 R P 1 R P 0 R P 0 R P 0 R P 0 R P 0 R P X X X X X X X X X X X X X X X X X X X X F E R F E R F E R F E R F E R L N A L N A L N A L N A L N A C A D C A D C A D C A D C A D C D A C D A C D A C D A C D A A...

Page 13: ...D t l u a f e D t l u a f e D t l u a f e D t l u a f e D h A 7 h C 2 h A 7 h C 2 h A 7 h C 2 h A 7 h C 2 h A 7 h C 2 e t a R C A D M C P e t a R C A D M C P e t a R C A D M C P e t a R C A D M C P e t a R C A D M C P 5 1 R S 5 1 R S 5 1 R S 5 1 R S 5 1 R S 4 1 R S 4 1 R S 4 1 R S 4 1 R S 4 1 R S 3 1 R S 3 1 R S 3 1 R S 3 1 R S 3 1 R S 2 1 R S 2 1 R S 2 1 R S 2 1 R S 2 1 R S 1 1 R S 1 1 R S 1 1 R ...

Page 14: ... 1 D 5 1 D 4 1 D 4 1 D 4 1 D 4 1 D 4 1 D 3 1 D 3 1 D 3 1 D 3 1 D 3 1 D 2 1 D 2 1 D 2 1 D 2 1 D 2 1 D 1 1 D 1 1 D 1 1 D 1 1 D 1 1 D 0 1 D 0 1 D 0 1 D 0 1 D 0 1 D 9 D9 D9 D9 D9 D 8 D8 D8 D8 D8 D 7 D7 D7 D7 D7 D 6 D6 D6 D6 D6 D 5 D5 D5 D5 D5 D 4 D4 D4 D4 D4 D 3 D3 D3 D3 D3 D 2 D2 D2 D2 D2 D 1 D1 D1 D1 D1 D 0 D0 D0 D0 D0 D t l u a f e D t l u a f e D t l u a f e D t l u a f e D t l u a f e D h 6 7 h 6...

Page 15: ... R S 9 1 R S 9 1 R S 9 1 R S 8 1 R S 8 1 R S 8 1 R S 8 1 R S 8 1 R S 7 1 R S 7 1 R S 7 1 R S 7 1 R S 7 1 R S 6 1 R S 6 1 R S 6 1 R S 6 1 R S 6 1 R S 5 1 R S 5 1 R S 5 1 R S 5 1 R S 5 1 R S 4 1 R S 4 1 R S 4 1 R S 4 1 R S 4 1 R S 3 1 R S 2 1 R S 2 1 R S 2 1 R S 2 1 R S 2 1 R S 1 1 R S 1 1 R S 1 1 R S 1 1 R S 1 1 R S 0 1 R S 0 1 R S 0 1 R S 0 1 R S 0 1 R S h 0 8 B B h 0 8 B B h 0 8 B B h 0 8 B B h 0...

Page 16: ...ead Thin Plastic Quad Flatpack LQFP ST 48 TOP VIEW PINS DOWN 1 12 13 25 24 36 37 48 0 019 0 5 BSC 0 276 7 00 BSC SQ 0 011 0 27 0 006 0 17 0 354 9 00 BSC SQ 0 063 1 60 MAX 0 030 0 75 0 018 0 45 0 008 0 2 0 004 0 09 0ⴗ MIN COPLANARITY 0 003 0 08 SEATING PLANE 0 006 0 15 0 002 0 05 7ⴗ 0ⴗ 0 057 1 45 0 053 1 35 ...

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