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Format is set to the correct encoding (twos complement by default). Repeat for the other channels.
If the FFT appears normal but the performance is poor, check the following:
Make sure that an appropriate filter is used on the analog input.
●
Make sure that the signal generators for the clock and the analog input are clean (low phase noise).
●
Change the analog input frequency slightly if noncoherent sampling is being used.
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Make sure that the SPI configuration file matches the product being evaluated.
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If the FFT window remains blank after Run in VisualAnalog (see Figure 11) is clicked, do the following:
Make sure that the evaluation board is securely connected to the
board.
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Make sure that the FPGA has been programmed by verifying that the DONE LED is illuminated on
●
board. If this LED is not illuminated, make sure that the U4 switch on the
board is in the correct position for USB CONFIG.
Make sure that the correct FPGA program was installed by clicking the Settings icon in the ADC
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Data Capture block in VisualAnalog. Then select the FPGA tab and verify that the proper FPGA bin
file is selected for the part.
If VisualAnalog indicates that the FIFO Capture timed out, do the following:
Make sure that all power and USB connections are secure.
●
Make sure that the Poll Full Flag checkbox is checked under ADC Capture Settings in Visual
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