background image

 

Rev 13 May 2013 17:57 | Page 11

via SPI.

 Figure 9. SPI Controller, CLOCK

DIVIDE(B) Box
Note that other settings can be changed on the ADCBase 0 tab (see Figure 9) and the ADC A,

4.

ADC BADC C, and ADC D tabs (see Figure 10) to set up the part in the desired mode. The
ADCBase 0 tab settings affect the entire part, whereas the settings on the ADC AADC BADC C,
and ADC D tabs affect the selected channel only. See the appropriate part data sheet, the 

AN-878

Application Note

High Speed ADC SPI Control Software, and the 

AN-877 Application Note

,

Interfacing to High Speed ADCs via SPI, for additional information on the available settings.

 Figure 10. SPI Controller, Example

ADC A Page
Click the Run button in the VisualAnalog toolbar (see Figure 11).

5.

 Figure 11. Run Button (Encircled in

Red) in VisualAnalog Toolbar, Collapsed Display

Adjusting the Amplitude of the Input Signal

The next step is to adjust the amplitude of the input signal for each channel as follows:

Summary of Contents for AD9253

Page 1: ...perate these parts in their various modes and configurations The application software used to interface with the devices is also described The AD9653 AD9253 and AD9633 data sheets provide additional i...

Page 2: ...878 Application Note High Speed ADC SPI Control Software AN 877 Application Note Interfacing to High Speed ADCs via SPI AN 835 Application Note Understanding ADC Testing and Evaluation Design and Inte...

Page 3: ...1 shows the typical bench characterization setup used to evaluate AC performance It is critical that the signal sources used for the analog input and clock have very low phase noise 1 ps rms jitter to...

Page 4: ...e desired frequency and amplitude see the Specifications section in the data sheet of the respective part When connecting the analog input source use of a multipole narrow band band pass filter with 5...

Page 5: ...ate reference voltages from 1 0 V to 1 3 V the AD9253 and AD9633 reference voltage is specified to be 1 0 V J204 Use this jumper to power down the ADC Using the SPI the PDWN pin can be configured to b...

Page 6: ...ovided by the ADR130 This external reference can be connected to the ADC by connecting Pin 4 to Pin 6 on Header J202 Alternatively if an external off board reference is desired connect Pin 2 to Pin1 o...

Page 7: ...J802 labeled CLK PDWN To enable the power down feature add a shorting jumper across J204 at Pin 1 and Pin 2 to connect the PDWN pin to DRVDD Modes of Operation Standalone PIN Mode The AD9653 AD9253 AD...

Page 8: ...pe should be listed in the status 1 bar of the VisualAnalog New Canvas window Select the template that corresponds to the type of testing to be performed see Figure 3 where the AD9253 is shown as an e...

Page 9: ...lay Evaluation And Test Setting up the SPI Controller Software After the ADC data capture board setup is complete set up the SPI controller software using the following procedure Open the SPI controll...

Page 10: ...In the ADCBase 0 tab of the SPIController window find the CLOCK DIVIDE B box see Figure 3 9 If using the clock divider use the drop down box to select the correct clock divide ratio if necessary For...

Page 11: ...he selected channel only See the appropriate part data sheet the AN 878 Application Note High Speed ADC SPI Control Software and the AN 877 Application Note Interfacing to High Speed ADCs via SPI for...

Page 12: ...el D 2 Click the disk icon within the VisualAnalog Graph AD9253 FFT window to save the 3 performance plot data as a csv formatted file See Figure 13 for an example Figure 13 Typical FFT AD9253 Trouble...

Page 13: ...do the following Make sure that the evaluation board is securely connected to the HSC ADC EVALCZ board Make sure that the FPGA has been programmed by verifying that the DONE LED is illuminated on the...

Reviews: