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Rev 13 May 2013 17:57 | Page 4

on-board LDOs. This enables the user to bias each section of the board individually. Use P102 and
P103 to connect a different supply for each section. A 1.8 V, 0.5 A supply is needed for 1.8V_AVDD
and 1.8V_DRVDD. Although the power supply requirements are the same for AVDD and DRVDD, it is
recommended that separate supplies be used for both analog and digital domains. The SPI and its
level shifters and alternate clock options require a separate 3.3 V, 0.5 A analog supply.

Two additional supplies, 5V_AVDD and 3V_AVDD, are used to bias the optional input path amplifiers
and optional 

AD9517-3

 clock chip. If used, these supplies should each have 0.5 A current capability.

Input Signals

When connecting the ADC clock and analog source, use clean signal generators with low phase noise,
such as the Rohde & Schwarz SMA, or HP 8644B signal generators or an equivalent. Use a 1 m
shielded, RG-58, 50 Ω coaxial cable for connecting to the evaluation board. Enter the desired
frequency and amplitude (see the Specifications section in the data sheet of the respective part).
When connecting the analog input source, use of a multipole, narrow-band band-pass filter with 50 Ω
terminations is recommended. Analog Devices uses band-pass filters from TTE and K&L Microwave,
Inc. Connect the filters directly to the evaluation board.

If an external clock source is used, it should also be supplied with a clean signal generator as
previously specified. Analog Devices evaluation boards typically can accept ~2.8 V p-p or 13 dBm sine
wave input for the clock.

Output Signals

The default setup uses the Analog Devices high speed converter evaluation platform (

HSC-ADC-EVALCZ

) for data capture. The serial LVDS outputs from the ADC are routed to Connector

P1002 using 100 Ω differential traces. For more information on the data capture board and its optional
settings, visit 

www.analog.com/hsadcevalboard

.

Jumper Settings

Set the jumper settings/link options on the evaluation board for the required operating modes before
powering on the board. The functions of the jumpers are described in Table 1. Figure 2 shows the
default jumper settings.

Table 1. Jumper Settings

Summary of Contents for AD9253

Page 1: ...perate these parts in their various modes and configurations The application software used to interface with the devices is also described The AD9653 AD9253 and AD9633 data sheets provide additional i...

Page 2: ...878 Application Note High Speed ADC SPI Control Software AN 877 Application Note Interfacing to High Speed ADCs via SPI AN 835 Application Note Understanding ADC Testing and Evaluation Design and Inte...

Page 3: ...1 shows the typical bench characterization setup used to evaluate AC performance It is critical that the signal sources used for the analog input and clock have very low phase noise 1 ps rms jitter to...

Page 4: ...e desired frequency and amplitude see the Specifications section in the data sheet of the respective part When connecting the analog input source use of a multipole narrow band band pass filter with 5...

Page 5: ...ate reference voltages from 1 0 V to 1 3 V the AD9253 and AD9633 reference voltage is specified to be 1 0 V J204 Use this jumper to power down the ADC Using the SPI the PDWN pin can be configured to b...

Page 6: ...ovided by the ADR130 This external reference can be connected to the ADC by connecting Pin 4 to Pin 6 on Header J202 Alternatively if an external off board reference is desired connect Pin 2 to Pin1 o...

Page 7: ...J802 labeled CLK PDWN To enable the power down feature add a shorting jumper across J204 at Pin 1 and Pin 2 to connect the PDWN pin to DRVDD Modes of Operation Standalone PIN Mode The AD9653 AD9253 AD...

Page 8: ...pe should be listed in the status 1 bar of the VisualAnalog New Canvas window Select the template that corresponds to the type of testing to be performed see Figure 3 where the AD9253 is shown as an e...

Page 9: ...lay Evaluation And Test Setting up the SPI Controller Software After the ADC data capture board setup is complete set up the SPI controller software using the following procedure Open the SPI controll...

Page 10: ...In the ADCBase 0 tab of the SPIController window find the CLOCK DIVIDE B box see Figure 3 9 If using the clock divider use the drop down box to select the correct clock divide ratio if necessary For...

Page 11: ...he selected channel only See the appropriate part data sheet the AN 878 Application Note High Speed ADC SPI Control Software and the AN 877 Application Note Interfacing to High Speed ADCs via SPI for...

Page 12: ...el D 2 Click the disk icon within the VisualAnalog Graph AD9253 FFT window to save the 3 performance plot data as a csv formatted file See Figure 13 for an example Figure 13 Typical FFT AD9253 Trouble...

Page 13: ...do the following Make sure that the evaluation board is securely connected to the HSC ADC EVALCZ board Make sure that the FPGA has been programmed by verifying that the DONE LED is illuminated on the...

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