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Rev 03 Jun 2015 18:39 | Page 4

their various modes and configurations. Figure 1 shows the typical bench characterization setup used
to evaluate ac performance. It is critical that the signal sources used for the analog input and clock
have very low phase noise (ideally ~100 fs rms jitter) to realize the optimum performance of the
signal chain. Proper filtering of the analog input signal to remove harmonics and lower the integrated
or broadband noise at the input is necessary to achieve the specified noise performance.

See 

Schematics, layout files, bill of materials

 for schematics and layout diagrams.

Power Supplies

This evaluation board comes with a wall-mountable switching power supply that provides a 6 V, 2 A
maximum output. Connect the supply to a 100 V ac to 240 V ac, 47 Hz to 63 Hz wall outlet. The
output from the supply is provided through a 2.1 mm inner diameter jack that connects to the printed
circuit board (PCB) at P101. The 6 V supply is fused and conditioned on the PCB before connecting to
the low dropout linear regulators that supply the proper bias to each of the various sections on the
board.

The evaluation board can be powered in a nondefault condition using external bench power supplies.
To do this, remove E101, E102, E103, E105, E107, E108, and E114 ferrite beads to disconnect the
bench supply traces from the on-board LDOs. Note that in some board configurations, some of these
ferrite beads might already be uninstalled.

P102 and P103 need to be installed to connect external bench supplies to the board and E109, E110,
E111, E112, and E113 need to be populated to connect P102 and P103 to the board power domains. A
1.8 V, 0.5 A supply is needed for P102 Pin 5 (1.8V_DUT_AVDD). The supplies for P103 Pin 1
(DUT_DRVDD) and P103 Pin3 (AUX_DVDD) can be any voltage from 1.8 V to 3.3 V. These two supplies
can be shared or separate but if they are separate, the voltages on each must match the other.

Two additional supplies, 3.3V_CLK and 3.3V_AMPVDD, are used to bias the optional input path
amplifiers, SPI buffers, and optional 

AD9517-4

 clock chip. If used, each of these supplies need at least

a 0.5 A current capability.

Input Signals

When connecting the ADC clock and analog source, use clean signal generators with low phase noise,
such as the Rohde & Schwarz SMA, or an equivalent. Use a shielded, RG–58, 50 Ω coaxial cable
(optimally 1 m or shorter) for connecting to the evaluation board. Enter the desired frequency and
amplitude (see the Specifications section in the ADC data sheet). When connecting the analog input
source, use of a multipole, narrow-band band-pass filter with 50 Ω terminations is recommended.
Analog Devices uses band-pass filters from TTE and K&L Microwave, Inc. Connect the filters directly to
the evaluation board.

When an external clock source is used, it must be supplied with a clean signal generator, as
previously specified for the analog input signals. Analog Devices evaluation boards typically accept
~2.8 V p-p or 13 dBm sine wave input for the clock. If an external off-board clock source is used,

Summary of Contents for AD9266

Page 1: ...ication software used to interface with the devices is also described The AD9266 AD9649 AD9629 and AD9609 data sheets provide additional information and should be consulted when using the evaluation b...

Page 2: ...Evaluation Tool Version 1 0 User Manual AN 878 Application Note High Speed ADC SPI Control Software AN 877 Application Note Interfacing to High Speed ADCs via SPI AN 835 Application Note Understanding...

Page 3: ...of the HSC ADC EVALCZ is in the 2 5V position On the ADC evaluation board confirm that the jumpers are installed as shown in Figure 2 The 5 configuration in Figure 2 enables SPI control of the device...

Page 4: ...ds might already be uninstalled P102 and P103 need to be installed to connect external bench supplies to the board and E109 E110 E111 E112 and E113 need to be populated to connect P102 and P103 to the...

Page 5: ...ls power down and standby modes In the case where MODE_OR is configured as an input connecting Pin 2 to Pin 3 invokes the programmed pin function see the product datasheet for more information J302 J3...

Page 6: ...llowed on the AD9266 80EBZ and the AD9649 80EBZ boards Power Connect the switching power supply that is supplied in the evaluation kit between a rated 100 V ac to 240 V ac 47 Hz to 63 Hz wall outlet a...

Page 7: ...k frequency remove CR601 to preserve the slew rate of the clock signal The AD9266 80EBZ AD9649 80EBZ AD9629 80EBZ and AD9609 80EBZ boards are set up to be clocked through the transformer coupled input...

Page 8: ...information on the standalone pin mode is provided in the AD9266 AD9649 AD9629 and AD9609 data sheets Default Mode To operate the device under test DUT using the SPI follow the jumper settings for J30...

Page 9: ...mmed If VisualAnalog does not prompt for programming the FPGA select the ADC Data Capture Settings window and click on the Capture Board tab In the FPGA box select program to configure the FPGA Figure...

Page 10: ...ng the following procedure Open the SPI controller software by going to the Start menu or by double clicking the 1 SPIController software desktop icon If prompted for a configuration file select the a...

Page 11: ...Rev 03 Jun 2015 18 39 Page 11 controller configuration file is loaded see Figure 7 Figure 7 SPI Controller CHIP ID 1 Box Click the New DUT button in the SPIController window see Figure 8 2...

Page 12: ...own menu to select the correct clock divide ratio as desired If there is any interruption of the ADC clock during power up or during operation a digital reset may be needed to reinitialize the ADC Fig...

Page 13: ...peed ADCs via SPI for additional information on the available settings Click the Run or Continuous Run button in the VisualAnalog toolbar see Figure 11 5 Figure 11 Run Continuous Run Buttons Encircled...

Page 14: ...he HSC ADC EVALCZ Check that the USB cable is properly connected from the PC to the HSC ADC EVALCZ The LED on the VisualAnalog ADCDataCapture block should be green If it is red push the USB button on...

Page 15: ...g input frequency slightly That the SPI configuration file matches the product being evaluated If the FFT window remains blank after Run in VisualAnalog see Figure 12 is clicked do the following Make...

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