Rev 03 Jun 2015 18:39 | Page 7
RBIAS
DUT_RBIAS has a default value of 10 kΩ (R203) to ground and is used to set the ADC core bias current.
Note that using other than a 10 kΩ, 1% resistor for DUT_RBIAS (R203) may degrade the performance
of the device.
Clock
The default clock input circuit is derived from a simple transformer coupled circuit using a high
bandwidth 1:1 impedance ratio transformer (T601) that adds minimal jitter to the clock path. The
clock input is 50 Ω terminated and ac-coupled to handle single-ended sinusoidal inputs. The
transformer converts the single-ended input to a differential signal that is clipped by CR601 before
entering the ADC clock inputs. The
ADCs are equipped with an
internal 8:1 clock divider to facilitate use with higher frequency clocks. When using the internal
divider and a higher input clock frequency, remove CR601 to preserve the slew rate of the clock
signal.
,
,
boards are set up to be
clocked through the transformer coupled input network from the crystal oscillator, Y601. If a different
clock source is needed, remove C610 (optional) and place a jumper between Pin 2 and Pin 3 of J605 to
disable the oscillator and connect the external clock source to the SMA connector, J602 (labeled
).
Modes of Operation
Standalone (PIN) Mode
ADCs can operate in pin mode if there is no need to program
and change the default modes of operation via the SPI. For applications that do not require SPI mode
operation, the CSB pin is tied to 1.8V_DUT_AVDD by removing any jumper on Pin 8 of J302. In this
configuration, the SDIO/PDWN pin controls the power-down function, and the SCLK/DFS pin controls
the digital output format.
Table 2 and Table 3 specify the settings for pin mode operation. (These settings apply only when CSB
is tied high, that is, J302 Pin 8 has no jumper.)
