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Rev 13 Nov 2013 01:53 | Page 4

The evaluation board provides the support circuitry required to operate the 

AD9681

 in its various

modes and configurations. Figure 1 shows the typical bench characterization setup used to evaluate
AC performance. It is critical that the signal sources used for the analog input and clock have very low
phase noise (ideally ~100 fs rms jitter) to realize the optimum performance of the signal chain. Proper
filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise
at the input is necessary to achieve the specified noise performance.

See 

AD9681 Design Support <Coming Soon>

 for the complete schematics and layout diagrams.

These diagrams demonstrate the routing and grounding techniques that should be applied at the
system level when designing application boards using these converters.

Power Supplies

This evaluation board comes with a wall-mountable switching power supply that provides a 6V, 2A
maximum output. Connect the supply to a 100V ac to 240V ac, 47Hz to 63Hz wall outlet. The output
from the supply is provided through a 2.1mm inner diameter jack that connects to the printed circuit
board (PCB) at P101. The 6V supply is fused and conditioned on the PCB before connecting to the low
dropout linear regulators that supply the proper bias to each of the various sections on the board.

The evaluation board can be powered in a nondefault condition using external bench power supplies.
To do this, remove the E102, E103, E110, and E113 ferrite beads to disconnect the on-board LDOs
from the power planes. Note that in some board configurations some of these might already be
uninstalled. P102 and P103 headers can be installed to facilitate connection of external bench
supplies to the board. E106, E107, E108 and E109 need to be populated to connect P102 and P103 to
the board power domains. A 1.8V , 0.5A supply is needed for both 1.8V_DUT_AVDD and 1.8V_DRVDD.
Although the voltage requirements are the same for 1.8V_DUT_AVDD and 1.8V_DRVDD, it is
recommended that separate supplies be used for each of these.

Two additional supplies, 3.3V_CLK and 1.8V_DVDD, are used to power additional on board circuitry. If
used, these supplies should each have at least 0.5A current capability.

Input Signals

When connecting the ADC clock and analog source, use clean signal generators with low phase noise,
such as the Rohde & Schwarz SMA, or an equivalent. Use a shielded, RG-58, 50Ω coaxial cable
(optimally 1 m or shorter) for connecting to the evaluation board. Enter the desired frequency and
amplitude (see the Specifications section in the data sheet). When connecting the analog input source,
use of a multipole, narrow-band band-pass filter with 50Ω terminations is recommended. Analog
Devices uses band-pass filters from TTE and K&L Microwave, Inc. Connect the filters as close to the
evaluation board as possible.

If an external clock source is used instead of the onboard crystal oscillator, it should also be supplied
with a clean signal generator as previously specified for the analog input signals. Analog Devices
evaluation boards typically can accept ~2.8V p-p or 13 dBm sine wave input for the clock at the board
SMA clock connector. If an external off-board clock source is used, remove the jumper on J804, and

           

Summary of Contents for AD9681

Page 1: ...the support circuitry required to operate the ADC in its various modes and configurations The application software used to interface with the device is also described The AD9681 data sheet provides a...

Page 2: ...on board reference off board reference VisualAnalog and SPIController software interfaces Helpful Documents AD9681 data sheet High speed ADC FIFO evaluation kit HSC ADC EVALDZ HSC ADC EVALDZ Wiki Guid...

Page 3: ...oard as follows Connect the evaluation board to the data capture board as shown in Figure 1 1 On the ADC evaluation board confirm that the jumpers are installed as shown in Figure 2 2 Connect one 6V 2...

Page 4: ...ect the on board LDOs from the power planes Note that in some board configurations some of these might already be uninstalled P102 and P103 headers can be installed to facilitate connection of externa...

Page 5: ...DWN pin can be configured to invoke the STBY standby function instead of power down P1 This jumper sets the ADC for SPI communications with the HSC ADC EVALDZ Connect Pin 1 to Pin 2 for SDIO Pin 4 to...

Page 6: ...ed on the AD9681 125EBZ board Power Connect the switching power supply that is supplied in the evaluation kit between a rated 100V ac to 240V ac 47Hz to 63Hz wall outlet and P101 Analog Input The eigh...

Page 7: ...h higher frequency clocks When using the internal divider and a higher input clock frequency remove CR801 to preserve the slew rate of the clock signal The AD9681 125EBZ board is set up to be clocked...

Page 8: ...e the device under test DUT using the SPI follow the jumper settings for P1 as shown in Table 1 How To Use The Software For Testing Setting up the ADC Data Capture The installers for VisualAnalog and...

Page 9: ...e 4 VisualAnalog Default Configuration Message To change features to settings other than the default settings click the Expand Display button 3 located on the bottom right corner of the window see Fig...

Page 10: ...to the Start menu or by double clicking the 1 SPIController software desktop icon If prompted for a configuration file select cfg file whose name begins with AD9681 If not prompted check the title ba...

Page 11: ...Rev 13 Nov 2013 01 53 Page 11 Figure 7 SPI Controller CHIP ID 1 Box Click the New DUT button in the SPIController window see Figure 8 2...

Page 12: ...ivider use the drop down box to select the correct clock divide ratio if necessary If there is any interruption of the ADC clock during power up or during operation a Digital Reset may be needed to re...

Page 13: ...Rev 13 Nov 2013 01 53 Page 13 Figure 9 SPI Controller CLOCK DIVIDE B Box Figure...

Page 14: ...settings affect all channels on both ADC banks The settings in the ADC A through ADC D will likewise affect their respective channels in both banks For example with the All button pushed settings in...

Page 15: ...so that the fundamental is at the desired level Examine 1 the Fund Power reading in the left panel of the VisualAnalog Graph AD9681 FFT window see Figure 13 Figure 13 Graph Window of VisualAnalog Repe...

Page 16: ...ter matches the data format selected in the SPIController ADCBase0 OUTPUT MODE 14 window Repeat for the other channels If the FFT appears normal but the performance is poor check the following Make su...

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