Rev 13 Nov 2013 01:53 | Page 7
to ~200 MHz.
RBIAS
RBIAS has a default setting of 10 kΩ (R205 and R288) to ground and is used to set the ADC core bias
current. Note that using a resistor value other than 10kΩ, 1% resistors for RBIAS1 and RBIAS2 may
degrade the performance of the device.
Clock
The default clock input circuit is derived from a simple transformer-coupled circuit using a high
bandwidth 1:1 impedance ratio transformer (T801) that adds negligible jitter to the clock path. The
clock input is 50 Ω terminated and ac-coupled to handle single-ended sinusoidal inputs. The
transformer converts the single-ended input to a differential signal that is clipped by CR801 before
entering the ADC clock inputs. The
ADC is equipped with an internal clock divider
(programmable divide ratios of 1 through 8) to facilitate usage with higher frequency clocks. When
using the internal divider and a higher input clock frequency, remove CR801 to preserve the slew rate
of the clock signal.
board is set up to be clocked through the transformer-coupled input network
from the crystal oscillator, Y801. If a different clock source is desired, remove C810 (optional) and
Jumper J804 to disable the oscillator from running and connect the external clock source to the SMA
connector, J802 (labeled CLK+).
Modes of Operation
Standalone (PIN) Mode
ADC can operate in pin mode if there is no need to program and change the default
modes of operation via the SPI. For applications that do not require SPI mode operation, the CSB1 and
CSB2 pins are tied to 1.8V_DVDD by removing jumpers on Pin 8 and Pin 11 of P1. In this configuration
SDIO/OLM (P1 Pin 2) controls the output lane mode, and SCLK/DTP (P1 Pin 5) controls the digital
output test pattern. Table 2 and Table 3 specify the settings for pin mode operation.
Table 2. Digital Output Format Pin Settings
