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designed or reviewed by Analog Devices, care should  be  taken  to  ensure  that  these  will  meet 

your needs before purchase. While ADI will always provide chip level support on  the 
EngineerZone™

 [http://ez.analog.com/]

, board level, or reference design support is given by the 

manufacture or creator of the specific materials. 

References to manufacturer or third party software, websites, or to any specific commercial or 
non-commercial products are suggestions only and do not necessarily constitute or imply an 

endorsement, recommendation, or favoring by Analog Devices. 

22 Sep 2011 16:30 

4 x independent DVB-T channels, RF output (0 to 1.250 GHz) from MVD Cores

 

[http://www.mvd-fpga.com/cores/en/digilent_AD9739A_xilinx_eval.html]

4 x independent ATSC channels, RF output (0 to 1.250 GHz)from MVD Cores

 

[http://www.mvd-fpga.com/cores/en/digilent_AD9739A_xilinx_eval.html]

4 x independent J.83B channels, RF output (0 to 1.250 GHz) from MVD Cores

 

[http://www.mvd-fpga.com/cores/en/digilent_AD9739A_xilinx_eval.html]

4 x independent DVB-C J.83A/C channels, RF output (0 to 1.250 GHz) from MVD Cores

 

[http://www.mvd-fpga.com/cores/en/digilent_AD9739A_xilinx_eval.html]

Tar file contents

The tar file contains, in most cases, the following files and/or directories. To rebuild the 
reference design simply double click the XMP file and run the tool. To build SDK, select a 
workspace and use the C file to build the elf file. Please refer to Xilinx EDK documentation

 

[http://www.xilinx.com/support/documentation/dt_edk_edk13-2.htm]

 for details. 

license.txt 

ADI license & copyright information. 

system.bsb  BSB wizard file. 

system.mhs MHS file. 

system.xmp  XMP file (use this file to build the reference design). 

data/ UCF 

file 

and/or 

DDR MIG project files. 

docs/ 

Documentation files (Please note that this wiki page is the documentation for the reference design). 

ise/ 

ISE project file(s) (for stand alone build) and/or simulation. 

pcores/ Reference 

design core file(s) (Xilinx EDK). 

scripts/

Individual scripts for platgen, xst, xflow etc. for command line run. 

sw/ 

Software (Xilinx SDK) & bit file(s). 

tb/ 

Test bench source file(s). 

More information

Purchase AD9739A-FMC-EBZ

 [http://www.analog.com/en/digital-to-analog-converters/da-

converters/ad9739a/products/EVAL-AD9739A/eb.html]

VITA's FMC info

 [http://www.vita.com/fmc.html]

ask questions about the FPGA reference design

 [http://ez.analog.com/community/fpga]

ask questions about the AD9739A

 [http://ez.analog.com/community/data_converters/high-

speed_dacs]

Page 11 of 12

AD9739A Native FMC Card / Xilinx Reference Designs [Analog Devices Wiki]

5/22/2012

http://wiki.analog.com/resources/fpga/xilinx/fmc/ad9739a?force_rev=1

Summary of Contents for AD9739A

Page 1: ...x Reference Designs Introduction The AD9739A http www analog com AD9739A is a 14 bit 2 5 GSPS high performance RF DAC capable of synthesizing wideband signals with up to 1 25GHz of bandwidth This refe...

Page 2: ...bugs below It was designed and meets the needs of prototyping platforms and will work with FPGA Development systems which include an FMC connector It may not mechanically fit on other ANSI VITA 57 1 c...

Page 3: ...tm http www xilinx com products boards ml605 reference_designs htm for details To begin connect the AD9739A FMC EBZ board to the FMC LPC connector of ML605 board see image below If using KC705 use FMC...

Page 4: ...nd then program the device If programming was successful you should be seeing messages appear on the terminal as shown in figure below After programming the AD9739A and ADF4350 the program continously...

Page 5: ...ements for this card with the AD9739A running at 2 5GHz with carrier s centered at 980MHz Adjacent Channel Leakage Ratio ACLR is the ratio of the reconstructed signal power to the power measured in an...

Page 6: ...DK The SPI interface allows programming the ADF4350 and or AD9739A The provided SDK software shows the initial setup required for both the devices for a 2 5GHz DAC clock with a 300MHz single tone DDS...

Page 7: ...the AD9739A http www analog com AD9739A 1 6GHz to 2 5GHz Alternatively an external clock can be provided via the SMA CLKIN J3 jack To enable this clock path jumper CLK SRC P3 must be moved to the SMA...

Page 8: ...39A datasheet In the interest of continuous quality improvements the images below may not exactly match your version of the software SPI Settings and Powerdown Reset These bits shown in Figure 12 cont...

Page 9: ...Invalid Search GB sets a GB from the beginning and end of the Mu Delay line in which the Mu controller will not enter into unless it does not find a valid phase outside the GB Register 0x29 bits 0 4...

Page 10: ...ce Code Download the AD9739A USB SPI Software and Drivers http www analog com en digital to analog converters da converters ad9739a products EVAL AD9739A eb html Design AD9739A FMC EBZ Schematic AD973...

Page 11: ...e following files and or directories To rebuild the reference design simply double click the XMP file and run the tool To build SDK select a workspace and use the C file to build the elf file Please r...

Page 12: ...om About This Site Wiki Sitemap eNewsletters 1995 2012 Analog Devices Inc and other contributors Page 12 of 12 AD9739A Native FMC Card Xilinx Reference Designs Analog Devices Wiki 5 22 2012 http wiki...

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