AD9776A/AD9778A/AD9779A
Rev. B | Page 26 of 56
3-WIRE INTERFACE
The 3-wire port is a flexible, synchronous serial communications
port allowing easy interface to many industry-standard micro-
controllers and microprocessors. The port is compatible with
most synchronous transfer formats, including both the
Motorola SPI and Intel® SSR protocols.
The interface allows read and write access to all registers
that configure the AD9776A/AD9778A/AD9779A. Single-
or multiple-byte transfers are supported, as well as MSB-first
or LSB-first transfer formats. Serial data input/output can be
accomplished through a single bidirectional pin (SDIO) or
through two unidirectional pins (SDIO/SDO).
The serial port configuration is controlled by Register 0x00,
Bits[7:6]. It is important to note that any change made to the
serial port configuration occurs immediately upon writing to
the last bit of this byte. Therefore, it is possible with a multibyte
transfer to write to this register and change the configuration in
the middle of a communication cycle. Care must be taken to
compensate for the new configuration within the remaining
bytes of the current communication cycle.
Use of a single-byte transfer when changing the serial port
configuration is recommended to prevent unexpected device
behavior.
As described in this section, all serial port data is transferred
to/from the device in synchronization with the SCLK pin. If
synchronization is lost, the device has the ability to asynchro-
nously terminate an I/O operation, putting the serial port
controller into a known state and, thereby, regaining synchro-
nization.
SDO
SPI
PORT
66
SDIO
67
SCLK
68
CSB
69
0
64
52
-04
9
Figure 52. 3-Wire Interface Port
GENERAL OPERATION OF THE SERIAL INTERFACE
There are two phases of a communication cycle with the
AD9776A/AD9778A/AD9779A. Phase 1 is the instruction cycle
(the writing of an instruction byte into the device), coinciding with
the first eight SCLK rising edges. The instruction byte provides
the serial port controller with information regarding the data
transfer cycle, which is Phase 2 of the communication cycle. The
Phase 1 instruction byte defines whether the upcoming data
transfer is a read or write, the number of bytes in the data transfer,
and the starting register address for the first byte of the data
transfer. The first eight SCLK rising edges of each communication
cycle are used to write the instruction byte into the device.
A logic high on the CSB pin followed by a logic low resets the
3-wire interface port timing to the initial state of the instruction
cycle. From this state, the next eight rising SCLK edges represent
the instruction bits of the current I/O operation, regardless of
the state of the internal registers or the other signal levels at the
inputs to the 3-wire interface port. If the 3-wire interface port is
in an instruction cycle or a data transfer cycle, none of the present
data is written.
The remaining SCLK edges are for Phase 2 of the communica-
tion cycle. Phase 2 is the actual data transfer between the device
and the system controller. Phase 2 of the communication cycle
is a transfer of one, two, three, or four data bytes, as determined
by the instruction byte. Using one multibyte transfer is preferred.
Single-byte data transfers are useful in reducing CPU overhead
when register access requires only one byte. Registers change
immediately upon writing to the last bit of each transfer byte.
INSTRUCTION BYTE
See Table 11 for information contained in the instruction byte.
Table 11. 3-Wire Interface Instruction Byte
MSB
LSB
I7
I6 I5 I4 I3 I2 I1 I0
R/W
N1 N0 A4 A3 A2 A1 A0
R/W, Bit 7 of the instruction byte, determines whether a read
or a write data transfer occurs after the instruction byte write.
Logic 1 indicates a read operation. Logic 0 indicates a write
operation.
N1 and N0, Bit 6 and Bit 5 of the instruction byte, determine
the number of bytes to be transferred during the data transfer
cycle. The translation for the number of bytes to be transferred
is listed in Table 12.
A4, A3, A2, A1, and A0—Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0,
respectively, of the instruction byte—determine the register that
is accessed during the data transfer portion of the communication
cycle. For multibyte transfers, this address is the starting byte
address. The remaining register addresses are generated by the
device, based on the LSB-first bit (Register 0x00, Bit 6).
Table 12. Byte Transfer Count
N1 N0 Description
0
0
Transfer one byte
0
1
Transfer two bytes
1
0
Transfer three bytes
1
1
Transfer four bytes
