Analog Devices AD9779 Preliminary Technical Data Download

Page: 18 / 34

AD9779

Preliminary Technical Data

Rev. PrD | Page 18 of 34

Aux DAC1 Sign

0: Positive
1: Negative

6 Aux

DAC1

Direction

0: Source
1: Sink

Aux DAC1 Sleep

0: Aux DAC1 on
1: Aux DAC 1 off

Auxiliary DAC1
Control and Data

1:0 Aux

DAC1

Gain

Adjustment

(9:8) MSB slice of 10 bit gain setting word for Aux DAC1

QDAC Gain

7:0 QDAC

Gain

Adjustment

(7:0) LSB slice of 10 bit gain setting word for QDAC

11111001

QDAC Sleep

0: QDAC on
1: QDAC off

6 QDAC

Power

Down

0: QDAC on
1: QDAC off

QDAC Gain and
Control

1:0 QDAC

Gain

Adjustment

(9:8) MSB slice of 10 bit gain setting word for QDAC

Auxiliary DAC2 Gain

7:0 Aux

DAC2

Gain

Adjustment

(7:0) LSB slice of 10 bit gain setting word for Aux DAC2

00000000

Aux DAC2 Sign

0: Positive

1: Negative

6 Aux

DAC2

Direction

0: Source
1: Sink

Aux DAC2 Sleep

0: Aux DAC1 on
1: Aux DAC 1 off

Auxiliary DAC2
Control and Data

1:0 Aux

DAC2

Gain

Adjustment

(9:8) MSB slice of 10 bit gain setting word for Aux DAC2

Cross Point Upper
Delay

7:0

Updelay

Value above zero for upper cross delay (bits 7,6, unused)

00000000

Cross Point Upper
Delay

7:0

Dndelay

Value below zero for lower cross delay (bits 7,6, unused)

00000000

7:3 Cross

Control

Clock Delay

Divide rate of CNTCLK by 2^(3:0), CNTCLK = 1/16 DAC clock rate

00000

Wiggle Delay for
Cross Point Control

2:0

Wiggle Delay

Time step in 2^(Wiggle Delay) CNTCLK cycles

000

Cross Run

0: Disables Cross Control loop
1: Enables Cross Control loop

Cross Status (read
only)

0: Control loop is lowering cross point

1: Control loop is raising cross point

Cross Done (read
only)

0: Control loop is chnaging cross point value
1: Control loop is holding cross point value

4:2

Cross Wiggle

(2:0) Number of iterations allowed in control loop

000

Cross Point Control

1:0

Cross Step

(1:0) Value to change cross point value per iteration (wiggle)

Analog Write

7:0

Analog Write

Provides extra writeable control registers for analog circuit

00000000

7:6

Mirror Roll off
Frequency

Mirror Roll off and
band gap Trim

2:0 Band

Gap

Trim

Temperature
Characteristic

000

Output stack headroom control

Overdrive (current density) trim (temperature packing)

Output Stack
headroom Control

Reference offset from VDD3V (vcas centering)

Analog Status

7:0

Analog Status

Provides extra status register for analog circuitry (unused, read only)

Summary of Contents for AD9779

Page 1: ...frequency It includes features optimized for direct conversion transmit applications including complex digital modulation and gain and offset compensation The DAC outputs are optimized to interface se...

Page 2: ...ers 13 Notes on Serial Port Operation 13 SPI Register Map 14 Internal Reference Full Scale Current Generation 22 Auxiliary DACs 22 Power Down and Sleep Modes 22 Internal PLL Clock Multiplier Clock Dis...

Page 3: ...Reference TBD FSR Full Scale Output Current 10 20 30 mA Output Compliance Range 1 0 V Output Resistance TBD k ANALOG OUTPUTS Output Capacitance TBD pF Offset TBD ppm C Gain TBD ppm C TEMPERATURE DRIF...

Page 4: ...tput Noise IoutFS 20mA TBD pA rtHz fDAC 100 MSPS fOUT 20 MHz 82 dBc fDAC 200 MSPS fOUT 50 MHz 82 dBc fDAC 400 MSPS fOUT 70 MHz 84 dBc SPURIOUS FREE DYNAMIC RANGE SFDR fDAC 800 MSPS fOUT 70 MHz 87 dBc...

Page 5: ...4 VREF Voltage Reference Output 25 P1D 9 Port 1 Data Input D9 75 I120 120 A Reference Current 26 P1D 8 Port 1 Data Input D8 76 VDDA33 3 3 V Analog Supply 27 P1D 7 Port 1 Data Input D7 77 VSSA Analog C...

Page 6: ...1D 0 P1D 1 P1D 2 P1D 3 VDDD18 VSSD P1D 4 P1D 5 P1D 6 P1D 7 P1D 8 P1D 9 27 26 P2D 7 P2D 8 P2D 9 P2D 10 50 49 AUX1_P VSSA VDDA33 VSSA VDDA33 CLK CLK VDDC18 VSSC VSSC 3 2 VDDC18 VSSC VSSC VDDC18 1 VDDC18...

Page 7: ...H 35 2315 H 22 H 34 0 H 23 H 33 3671 H 24 H 32 0 H 25 H 31 6642 H 26 H 30 0 H 27 H 29 20755 H 28 32768 Table 6 Halfband Filter 2 Lower Coefficient Upper Coefficient Integer Value H 1 H 23 2 H 2 H 22 0...

Page 8: ...Response to 4x Input Data Rate Dotted Lines Indicate 1dBRoll Off 4 3 2 1 0 1 2 3 4 100 90 80 70 60 50 40 30 20 10 0 10 Figure 4 AD9779 4x Interpolation Low Pass Response to 4x Input Data Rate Dotted...

Page 9: ...ut MHz SFDR dBm FDATA 100MSPS FDATA 160MSPS FDATA 200MSPS Figure 8 SFDR vs FOUT 1x Interpolation 50 55 60 65 70 75 80 85 90 95 100 0 20 40 60 80 100 Fout MHz SFDR dBm FDATA 100MSPS FDATA 160MSPS FDATA...

Page 10: ...FDATA 125MSPS FDATA 150MSPS FDATA 200MSPS Figure 14 Third Order IMD vs FOUT 4x Interpolation 50 60 70 80 90 100 0 50 100 150 200 250 300 350 400 450 Fout MHz IMD dBc 50MSPS 100MSPS FDATA 62 5MSPS 112...

Page 11: ...3 0 4 0 5 0 6 0 7 0 25 50 75 100 125 150 175 200 225 250 FDATA MSPS Power W 8x Interpolation Zero Stuffing 4x Interpolation Zero Stuffing 4x Interpolation 2x Interpolation Zero Stuffing 2x Interpolat...

Page 12: ...ow will reset the SPI port timing to the initial state of the instruction cycle This is true regardless of the present state of the internal registers or the other signal levels present at the inputs...

Page 13: ...rator increments for each byte of the multibyte communication cycle The AD9779 serial port controller data address will decrement from the data address written toward 0x00 for multibyte I O operations...

Page 14: ...e Sync Driver Enable Dac Clock Offset 2 0 00h Interrupt Register 06h 06 Data Delay IRQ Sync Delay IRQ Cross Control IRQ Data Delay IRQ Enable Sync Delay IRQ Enable Cross Control IRQ Enable 00h 07h 07...

Page 15: ...Delay 3 0 00h Cross Register 15h 20 Cross Run Cross Status Cross Done Cross Wiggle 2 0 Cross Step 1 0 00h Analog Write 16h 23 Analog Write 7 0 00h 17h 21 Mirror Roll Off 1 0 Band Gap Trim 2 0 00h Anal...

Page 16: ...Enable Q path for signal processing 1 Disable Q path data clocks disabled 0 3 Inverse Sinc Enable 0 Inverse sinc disabled 1 Inverse sinc disabled 0 2 DATACLK Invert 0 Output DATACLK same phase as inte...

Page 17: ...lter Bandwidth Tuning Recommended Settings See Table 14 for PLL Band Select values 000 PLL band select 00000 00111 100 PLL band select 01000 01111 110 PLL band select 10000 10111 111 PLL band select 1...

Page 18: ...0000 13 Cross Point Upper Delay 7 0 Dndelay Value below zero for lower cross delay bits 7 6 unused 00000000 7 3 Cross Control Clock Delay Divide rate of CNTCLK by 2 3 0 CNTCLK 1 16 DAC clock rate 0000...

Page 19: ...or off 1 Internal data generator on 0 1A MISR Control 2 0 Test Mode 000 Normal data port operation 001 111 To be defined test modes 000 1B MISR Signature Register 1 7 0 MISR Signature 31 24 Slice of 3...

Page 20: ...125 8 0Ah 2 2 5 3F 8_even 6 0 575 0 625 0 675 8 0Bh 3 3 6 3F 8_odd 5 0 6375 0 6875 0 7375 8 0Ch 0 4 6 2F 8_even 4 0 7 0 75 0 8 8 0Dh 1 5 6 2F 8_odd 3 0 7625 0 8125 0 8625 8 0Eh 2 6 7 F 8_even 2 0 825...

Page 21: ...0110 22 1032 1089 10101 21 1060 1119 10100 20 1089 1149 10011 19 1118 1179 10010 18 1148 1210 10001 17 1176 1239 10000 16 1206 1270 01111 15 1237 1302 01110 14 1268 1334 01101 13 1299 1366 01100 12 13...

Page 22: ...d scale is reversed 0 1024 gives IFS to 0 and they can be programmed for sourcing or sinking current When sourcing current the output compliance voltage is 0 1 5V and when sinking current the output c...

Page 23: ...he ratio of Reference Clock Input Data Rate The VCO runs optimally over the range 804MHz to 1800MHz so that N1 is used to keep the speed of the VCO in this range even though the DAC sample rate may be...

Page 24: ...es of up to 250MSPS the AD9779 has a fine timing feature Fine timing adjustments can be made by programming values into the DATA CLOCK DELAY register reg 03h 5 3 By changing the values in this registe...

Page 25: ...1 4 3 2 2 3 4 1 1 2 3 4 1 2 5 7 8 6 3 4 5 6 7 8 Figure 39 Nyquist Zones Figure 3 Figure 4 and Figure 5 show the low pass response of the digital filters with no modulation used By turning on the modu...

Page 26: ...ass band will now be centered at 3 5 FDATA However the signal will still remain at the same place in the spectrum The even odd mode capability allows the passband to be placed anywhere in the DAC Nyqu...

Page 27: ...Preliminary Technical Data AD9779 Rev PrD Page 27 of 34 EVALUATION BOARD SCHEMATICS Figure 47 AD9779 Eval Board Rev B Power Supply Decoupling and SPI Interface...

Page 28: ...AD9779 Preliminary Technical Data Rev PrD Page 28 of 34 Figure 48 AD9779 Eval Board Rev B Circuitry Local to AD9779...

Page 29: ...Preliminary Technical Data AD9779 Rev PrD Page 29 of 34 Figure 49 AD9779 Eval Board RevB AD8349 Quadrature Modulator...

Page 30: ...AD9779 Preliminary Technical Data Rev PrD Page 30 of 34 Figure 50 AD9779 Eval Board RevB DAC Clock Interface...

Page 31: ...Preliminary Technical Data AD9779 Rev PrD Page 31 of 34 Figure 51 AD9779 Eval Board RevB Input Port 1 Digital Input Buffers...

Page 32: ...AD9779 Preliminary Technical Data Rev PrD Page 32 of 34 Figure 52 AD9779 Eval Board RevB Input Port 2 Digital Input Buffers...

Page 33: ...Preliminary Technical Data AD9779 Rev PrD Page 33 of 34 Outline Dimensions...

Page 34: ...proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degr...

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