ADV7181B
Rev. B | Page 5 of 100
FUNCTIONAL BLOCK DIAGRAM
INPUT
MUX
DATA
PR
EPR
OC
ESSOR
DE
CIMATION AND
DOWNS
A
MP
LING
FILTERS
STANDARD DEFINITION PROCESSOR
LUMA
FILTER
LUMA
DIGITAL
FINE
CLAMP
GAIN
CONTROL
LUMA
R
ESA
M
P
LE
LUMA
2D
C
O
M
B
(4
H MAX
)
CHROMA
FILTER
CHROMA
DE
MOD
F
SC
RE
COV
E
R
Y
CHROMA
DIGITAL
FINE
CLAMP
GAIN
CONTROL
CHROMA
R
ESA
M
P
LE
CHROMA
2D
C
O
M
B
(4
H MAX
)
L-DNR
OUTPUT FORMATTER
SYN
C
E
X
T
RACT
LINE
LENGTH
PR
ED
IC
TOR
R
ESA
M
P
LE
CONTROL
AV
CODE
INSERTION
CTI
C-DNR
A/D
CLAMP
9
9
9
A/D
CLAMP
9
A/D
CLAMP
9
V
B
I DATA RE
COV
E
R
Y
GLOBAL CONTROL
SYN
TH
ESIZED
LLC CONTROL
MACROV
IS
ION
DE
TE
CTION
S
T
ANDARD
AUTODETECTION
FR
EE R
U
N
OUTP
UT CONTROL
SYN
C
PR
OC
ESSIN
G
A
N
D
CLOCK GE
NE
RATION
S
E
R
IAL INTE
RFACE
CONTROL AND V
B
I DATA
SC
LK
AIN1
–
AIN6
SD
A
ALS
B
ADV7181B
CONTROL
AND DATA
S
Y
NC AND
CLK CONTROL
16
HS
8
8
PIXEL
DATA
VS
FIELD
LLC
SFL
CV
BS
S-
VID
EO
YPrPb
6
INTRQ
04984-001
Figure 1.
