ADV7181B
Rev. B | Page 22 of 100
SRLS Select Raw Lock Signal, Address 0x51[6]
Using the SRLS bit, the user can choose between two sources for
determining the lock status (per Bits[1:0] in the Status 1 register).
•
The time_win signal is based on a line-to-line evaluation of
the horizontal synchronization pulse of the incoming
video. It reacts quite quickly.
•
The free_run signal evaluates the properties of the
incoming video over several fields, and takes vertical
synchronization information into account.
Setting SRLS to 0 (default) selects the free_run signal.
Setting SRLS to 1 selects the time_win signal.
FSCLE F
SC
Lock Enable, Address 0x51[7]
The FSCLE bit allows the user to choose whether the status of
the color subcarrier loop is taken into account when the overall
lock status is determined and presented via Bits[1:0] in Status
Register 1. This bit must be set to 0 when operating the
ADV7181B in YPrPb component mode to generate a reliable
HLOCK status bit.
When FSCLE is set to 0 (default), the overall lock status is only
dependent on horizontal sync lock.
When FSCLE is set to 1, the overall lock status is dependent on
horizontal sync lock and F
SC
Lock.
VS_COAST[1:0], Address 0xF9[3:2]
These bits are used to set VS free-run (coast) frequency.
Table 18. VS_COAST[1:0] Function
VS_COAST[1:0] Description
00 (default)
Auto coast mode – follows VS
frequency from last video input
01
Forces 50 Hz coast mode
10
Forces 60 Hz coast mode
11 Reserved
CIL[2:0] Count Into Lock, Address 0x51[2:0]
CIL[2:0] determines the number of consecutive lines for which
the lock condition must be true before the system switches into
the locked state, and reports this via Status 0[1:0]. It counts the
value in lines of video.
Table 19. CIL Function
CIL[2:0] Description
000 1
001 2
010 5
011 10
100 (default)
100
101 500
110 1000
111 100000
COL[2:0] Count Out-of-Lock, Address 0x51[5:3]
COL[2:0] determines the number of consecutive lines for which
the out-of-lock condition must be true before the system
switches into unlocked state, and reports this via Status 0[1:0]. It
counts the value in lines of video.
Table 20. COL Function
COL[2:0] Description
000 1
001 2
010 5
011 10
100 (default)
100
101 500
110 1000
111 100000
COLOR CONTROLS
These registers allow the user to control picture appearance,
including control of the active data in the event of video being
lost. These controls are independent of any other controls. For
instance, brightness control is independent from picture
clamping, although both controls affect the signal’s dc level.
CON[7:0] Contrast Adjust, Address 0x08[7:0]
This register allows the user to control contrast adjustment
of the picture.
Table 21. CON Function
CON[7:0] Description
0x80 (default)
Gain on luma channel = 1
0x00
Gain on luma channel = 0
0xFF
Gain on luma channel = 2
SD_SAT_Cb[7:0] SD Saturation Cb Channel,
Address 0xE3[7:0]
This register allows the user to control the gain of the Cb
channel only, which in turn adjusts the saturation of the picture.
Table 22. SD_SAT_Cb Function
SD_SAT_Cb[7:0] Description
0x80 (default)
Gain on Cb channel = 0 dB
0x00
Gain on Cb channel = −42 dB
0xFF
Gain on Cb channel = +6 dB
