ADV7181B
Rev. B | Page 41 of 100
Table 55. Recommended User Settings for NTSC (See Figure 21)
Register Register
Name
Write
0x31
Vsync Field Control 1
0x1A
0x32
Vsync Field Control 2
0x81
0x33
Vsync Field Control 3
0x84
0x34
Hsync Pos. Control 1
0x00
0x35
Hsync Pos. Control 1
0x00
0x36
Hsync Pos. Control 1
0x7D
0x37 Polarity
0xA1
0xE5 NTSV_V_Bit_Beg
0x41
0xE6 NTSC_V_Bit_End
0x84
0xE7 NTSC_F_Bit_Tog
0x06
ADVANCE BEGIN OF
VSYNC BY NVBEG[4:0]
DELAY BEGIN OF
VSYNC BY NVBEG[4:0]
VSYNC BEGIN
NVBEGSIGN
ODD FIELD?
0
1
NO
YES
NVBEGDELO
VSBHO
ADDITIONAL
DELAY BY
1 LINE
ADVANCE BY
0.5 LINE
1
0
1
0
NVBEGDELE
VSBHE
ADDITIONAL
DELAY BY
1 LINE
ADVANCE BY
0.5 LINE
1
0
1
0
NOT VALID FOR USER
PROGRAMMING
04984-
022
Figure 22. NTSC Vsync Begin
NVBEGDELO NTSC Vsync Begin Delay on Odd Field,
Address 0xE5[7]
When NVBEGDELO is 0 (default), there is no delay.
Setting NVBEGDELO to 1 delays Vsync going high on an odd
field by a line relative to NVBEG.
NVBEGDELE NTSC Vsync Begin Delay on Even Field,
Address 0xE5[6]
When NVBEGDELE is 0 (default), there is no delay.
Setting NVBEGDELE to 1 delays Vsync going high on an even
field by a line relative to NVBEG.
NVBEGSIGN NTSC Vsync Begin Sign, Address 0xE5[5]
Setting NVBEGSIGN to 0 delays the start of Vsync. Set for user
manual programming.
Setting NVBEGSIGN to 1 (default) advances the start of Vsync.
Not recommended for user programming.
NVBEG[4:0] NTSC Vsync Begin, Address 0xE5[4:0]
The default value of NVBEG is 00101, indicating the NTSC
Vsync begin position.
For all NTSC/PAL Vsync timing controls, both the V bit in the
AV code and the Vsync on the VS pin are modified.
