Analog Devices ADV8003 Hardware Manual Download

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ADV8003 Hardware Manual

Rev. B, August 2013

252

Packet Map
Address

Access Type

Register Name

Default Value

Byte Name

0xF2F7

R/W

spare2_pb20[7:0]

0b00000000

Data Byte 20

0xF2F8

R/W

spare2_pb21[7:0]

0b00000000

Data Byte 21

0xF2F9

R/W

spare2_pb22[7:0]

0b00000000

Data Byte 22

0xF2FA

R/W

spare2_pb23[7:0]

0b00000000

Data Byte 23

0xF2FB

R/W

spare2_pb24[7:0]

0b00000000

Data Byte 24

0xF2FC

R/W

spare2_pb25[7:0]

0b00000000

Data Byte 25

0xF2FD

R/W

spare2_pb26[7:0]

0b00000000

Data Byte 26

0xF2FE

R/W

spare2_pb27[7:0]

0b00000000

Data Byte 27

6.7.

SYSTEM MONITORING

6.7.1.

General Status and Interrupts

The ADV8003 utilizes both interrupts and status bits to indicate the status of internal operations and errors in the Tx core. These interrupt
and status are listed in

Table 52

Table 53

, and

Table 54

. Refer to Section

9.4 for details on the use of Tx interrupts.

Table 52: HDMI Tx Interrupt Bits in HDMI Tx Main Map Register 0xEC96

Bit Name

Bit Position

Description

hdcp_authenticated_int

1 (Second LSB)

When set to 1 it indicates that HDCP/EDID state machine transitioned from state 3 to state 4.
Once set, it remains high until it is cleared by setting it to 1.

edid_ready_int

When set to 1 it indicates that EDID has been read from Rx and is available in Packet Map.
Once set, it remains high until it is cleared by setting it to 1.

vsync_int

When set to 1 it indicates that leading edge detected on VSync input to Tx core. Once set, it

remains high until it is cleared by setting it to 1.

rx_sense_int

When set to 1 it indicates that TMDS clock lines voltage has crossed 1.8 V from high to low or

low to high. Once set, it remains high until it is cleared by setting it to 1.

hpd_int

When set to 1 it indicates that transition for high to low or low to high was detected on

input HPD signal. Once set, it remains high until it is cleared by setting it to 1.

Table 53: HDMI Tx Interrupt Bits in Main Map Register 0xEC97

Bit Name

Bit Position

Description

bksv_flag_int

When set to 1 it indicates that the KSVs from the downstream sink have been read and available in the

Memory Map. Once set, it remains high until it is cleared by setting it to 1.

hdcp_error_int

When set to 1 it indicates that the HDCP/EDID controller has reported an error. This error is available in
HDCP_CONTROLLER_ERROR. Once set, it remains high until it is cleared by setting it to 1.

Table 54: Status Bits in Main Map Register 0xEC42

Bit Name

Bit Position

Description

hpd_state

See description for

hpd_state

on page

246

rx_sense_state

See description for

rx_sense_state

on page

247

6.8.

EDID/HDCP CONTROLLER STATUS

The Tx core features an EDID/HDCP controller which handles EDID extraction from the downstream sink. This EDID/HDCP controller
also handles HDCP authentication with downstream sink. The tasks that the Tx EDID/HDCP controller performs are described in

Section

6.12 and Section

6.13.

The current state of the Tx EDID/HDCP controller can be read from the

hdcp_controller_state[3:0]

status field.

hdcp_controller_state[3:0]

, TX2 Main Map,

Address 0xF4C8[3:0] (Read Only)