ADV8003 Hardware Manual
Rev. B, August 2013
359
47Ω series termination resistors should be placed in the middle of the trace on the following signals:
•
Data bus signals – DDR_DQ31-DDR_DQ0
•
Data strobe signals – DDR_DQS3 DDR_DQS3B-DDR_DQS0 DDR_DQS0B
The DDR2 reference voltage (DDR_VREF) should be routed as far away as possible from other signals to avoid any variations on the
voltage. This trace should be wide. There should be a 100 nF decoupling cap close to the DDR2 reference voltage pins as well as the
ADV8003 reference pin.
Power Supply Bypassing
It is recommended to bypass each power supply pin with a 0.1 uF and a 10 nF capacitor where possible. The fundamental idea is to have a
bypass capacitor within 0.5 cm of each power pin.
Current should flow from the power plane to the capacitor to the power pin. The power connection should not be made between the
capacitor and the power pin. Generally, the best approach is to place a via underneath the 10 nF capacitor pads down to the power plane
(refer to
10nF
0.1uF
via to GND layer
and GND pin
via to VDD pin
VDD supply
Figure 137: Recommended Power Supply Decoupling
It is recommended to individually filter all supplies to prevent switching noise on some supplies coupling onto other more sensitive
supplies. For example, DVDD consumes a significant amount of current and will also suffer significant switching noise. DVDD must be
isolated from more sensitive supplies such as PVDD3, PVDD5 and PVDD6.
The DVDD and DVDD_DDR supplies should be connected to the same supply – PVDD_DDR should be filtered from DVDD to provide
a noise free power supply.
It is recommended to use a single ground plane for the ADV8003. Careful attention must be paid to the layout of any internal power
supply planes when traces run on adjacent layers – traces on a layer directly above or below a power supply layer must not cross between
two power supply planes as this will impact the return current paths.
shows the recommended decoupling for the ADV8003-8 parts to achieve optimum performance for 3 GHz modes from the
HDMI TX devices.
Summary of Contents for ADV8003
Page 366: ...ADV8003 Hardware Manual Rev B August 2013 366 Figure 144 ADV8003 Schematic Page 4...
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Page 395: ...ADV8003 Hardware Manual Rev B August 2013 395 Figure 173 ADV8003 Layout Page 2...
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