ADV8003 Hardware Manual
Rev. B, August 2013
360
Table 94: Recommended PSU Decoupling for ADV8003-8 Parts
PSU
Ball Number
Capacitance Required
Placement
AVDD3
G23
4 x 100nF
As close as possible to ADV8003
G23
1 x 10nF
As close as possible to ADV8003
N22
3 x 100nF
As close as possible to ADV8003
N22
1 x 10nF
As close as possible to ADV8003
W22
3 x 100nF
As close as possible to ADV8003
W22
1 x 10nF
As close as possible to ADV8003
n/a
10uF
Place on AVDD3 trace after the EMC filter
PVDD5
M21
2 x 100nF
As close as possible to ADV8003
M21
1 x 10nF
As close as possible to ADV8003
N21
2 x 100nF
As close as possible to ADV8003
N21
1 x 10nF
As close as possible to ADV8003
n/a
10uF
Place on PVDD5 trace after the EMC filter
PVDD6
V21
2 x 100nF
As close as possible to ADV8003
V21
1 x 10nF
As close as possible to ADV8003
W21
2 x 100nF
As close as possible to ADV8003
W21
1 x 10nF
As close as possible to ADV8003
n/a
10uF
Place on PVDD5 trace after the EMC filter
General Digital Inputs and Outputs
The trace length that the digital inputs/outputs have to sink/source should be minimized. Longer traces have higher capacitance, which
requires more current that can cause more internal digital noise. Shorter traces reduce the possibility of reflections. It is recommended to
route traces in the shortest trace length possible and keep the number of layer transitions to a minimum.
If possible, the digital output driver capacitance loading should be limited to less than 15 pF. This can be accomplished easily by keeping
traces short and by connecting the outputs to only one device. Loading the outputs with excessive capacitance increases the current
transients inside the ADV8003, creating more digital noise on its power supplies.
Particular attention must be paid to the routing of clock and sync signals, for example, PCLK, OSD_CLK, HS, OSD_HS, VS, OSD_VS,
DE, OSD_DE, XTALN, and XTALP. Any noise that gets onto these signals can add jitter to the system. Therefore, the trace length should
be minimized, and digital or other high frequency traces should not be run near it.
XTAL and Load Cap Value Selection
The ADV8003 requires a 27 MHz crystal.
shows an example of a reference clock circuit for the ADV8003. Special care must be
taken when using a crystal circuit to generate the reference clock for the ADV8003. Small variations in reference clock frequency can
impair the performance of the ADV8003.
Figure 138: Crystal Circuit
These guidelines are followed to ensure correct operation:
•
Use the correct frequency crystal (27 MHz recommended). Tolerance should be 50 ppm or better.
•
Know the C
load
for the crystal part number selected. The value of capacitors C1 and C2 must be matched to the C
load
for the
specific crystal part number in the user’s system.
47pF
X
T
A
L
27MHz
C1
C2
47pF
Summary of Contents for ADV8003
Page 366: ...ADV8003 Hardware Manual Rev B August 2013 366 Figure 144 ADV8003 Schematic Page 4...
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Page 395: ...ADV8003 Hardware Manual Rev B August 2013 395 Figure 173 ADV8003 Layout Page 2...
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