ADV8003 Hardware Manual
Rev. B, August 2013
438
REVISION HISTORY
04/13 – Rev. A to Rev. B
Removed ADI Confidential from footer.
04/13 – Rev. 0 to Rev. A
Removed the descriptionof the Subcarrier Phase Reset and Timing Reset Modes.
Removed mention of non-standard timing mode under Table 76
Removed Section 6.11.2 Audio from Serial Video Rx.
Corrected the I2C readbacks for the Chip ID registers to 0x1AD0 and 0x1AD1 in section 2.2.13
Corrected Figure 25 to read 720P EXOSD input.
Updated Appendix F to replace OSD_P with OSD_IN, which is consistant with the rest of the document.
Updated Appendix F to replace VID_P with P, which is consistant with the rest of the document.
Added a description of the vfe_input_id[3:0] control.
10/13 – Pr.2 to Rev. 0
Functional block diagram updated
Pinout diagrams updated
Unused pin list updated
Pixel mapping updated
Interrupts section updated
Charge injections section added
ARC clarified
DDR2 Interface clarified
10/12 – Pr. 1 to Pr. 2
ADV8003 pin outs updated
2.2.2.3 Section added
2.2.4.3 Updated
2.2.11 Modes which require manual configuration added
2.2.11 Example added
2.2.13 Silicon revision updated
2.2.14 New section on system configuration sequencing added
3 CEA modes not supported by the PVSP clarified
4 CEA modes not supported by the SVSP clarified
6.2 New Section detailing HDMI Tx reset strategy
6.13 Audio Return Channel confirmed as only working in common mode
Tables 47, 48 and 49 added
8.3 Updated
Appendix A Layout recommendations updated
Table 90 Added
Appendix E Updated
Appendix F Pin mapping updated
01/12 – Pr. 0 to Pr. 1
TMDS RX/HDMI Compatible Rx updated to Serial Video Rx
1.1. OVERVIEW updated
1.1.1. Digital Video Input updated
Updated functional block diagram
R_TX1 and R_TX2 resistors updated in pin list
2. ADV8003 TOP LEVEL CONTROL updated
Figure 11: ADV8003 Simplified Block Diagram updated
2.1.1. Selecting a Mode updated
Summary of Contents for ADV8003
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