ADV8003 Hardware Manual
Rev. B, August 2013
96
Function
vid_hs_pol
Description
0
Input HS polarity does not change
1
Input HS polarity gets inverted
vid_vs_pol
, IO Map,
Address 0x1B49[2]
This bit is used to set the polarity of the input VS timing signal.
Function
vid_vs_pol
Description
0
Input VS polarity does not change
1
Input VS polarity gets inverted
vid_de_pol
, IO Map,
Address 0x1B49[1]
This bit is used to set the polarity of the input DE enable signal.
Function
vid_de_pol
Description
0
Input DE polarity does not change
1
Input DE polarity gets inverted
vid_fld_pol
, IO Map,
Address 0x1B49[0]
This bit is used to set the polarity of the input Field (FLD) timing signal.
Function
vid_fld_pol
Description
0
Input FLD polarity does not change
1
Input FLD polarity gets inverted
is used to select the method by which the input video will be synchronized. This may be required when the ADV8003 is
used in conjunction with an MPEG decoder. MPEG decoders use embedded timing codes rather than using external HS and VS signals.
Similarly, other ADI decoders/HDMI Rxs can output video using embedded timing codes. This register should be programmed
depending on the timing method of the upstream IC.
Refer to
for more information on AV-codes.
vid_hs_vs_mode
, IO Map,
Address 0x1B4B[7]
This bit is used to select the method of input timing.
Function
vid_hs_vs_mode
Description
0
Use embedded SAV/EAV codes
1
Use external HS/VS synchronization signals
vid_av_pos_sel
, IO Map,
Address 0x1B4B[3]
This bit is used to select if the HS generated is consistent with EIA 861 timing or dependant on the embedded timing codes.
Summary of Contents for ADV8003
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