ADV8003 Hardware Manual
Rev. B, August 2013
253
This signal is used to readback the state of the EDID/HDCP controller.
Function
hdcp_controller_state[3
:0]
Description
0000
In reset (no hot plug detected)
0001
Reading EDID
0010
In idle state (waiting for HDCP request)
0011
Initializing HDCP
0100
HDCP enabled
0101
Initializing HDCP repeater
0110 - 1111
Reserved
6.9.
EDID/HDCP CONTROLLER ERROR CODES
If an HDCP authentication occurs between the ADV8003 and the downstream sink, the ADV8003 can trigger an interrupt to notify this
error to the user or the controlling CPU. The EDID/HDCP controller will then report the HDCP error code via the status field
. The error code is only valid when the
hdcp_error_int
interrupt bit is set to 1. The last error code will remain
in the HDCP/EDID controller error field even when the interrupt is cleared.
hdcp_controller_error[3:0]
, TX2 Main Map,
Address 0xF4C8[7:4] (Read Only)
This signal is used to readback the error code when the HDCP controller error interrupt HDCP_ERROR_INT is 1.
Function
hdcp_controller_error[3
:0]
Description
0000
No error
0001
Bad Rx BKSV
0010
Ri mismatch
0011
Pj mismatch
0100
I2C error (usually no acknowledge)
0101
Timed out waiting for downstream repeater
0110
Maximum cascade of repeaters exceeded
0111
SHA-1 hash check of KSV list fail
1000
Too many devices connected to the repeater tree
6.10.
VIDEO SETUP
6.10.1.
Input Format
The HDMI Tx core of the ADV8003 receives video data from the ADV8003 digital core via a 36-bit wide bus and four synchronization
signals: the pixel clock, the data enable, the horizontal and vertical synchronization signals. The HDMI Tx core always receives the video
data in a 4:4:4 and SDR format from the VSP core.
It is possible to send YCrCb 4:2:2 data from the TMDS RX directly to the HDMI TX. In which case register 0xEC15 must be set
appropriately in the TX main map.
vfe_input_id[3:0]
, TX1 Main Map,
Address 0xEC15[3:0]
This signal is used to specify the video input format.
Summary of Contents for ADV8003
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