ADV8003 Hardware Manual
Rev. B, August 2013
271
Function
spdif_sf[3:0]
Description
0000
44.1kHz
0001
NA
0010
48 kHz
0011
32kHz
0100
NA
0101
NA
0110
NA
0111
NA
1000
88.2kHz
1001
NA
1010
96kHz
1011
NA
1100
176.4kHz
1101
NA
1110
192kHz
1111
NA
6.11.2.3.
DSD Audio
The ADV8003 uses 1-bit Audio Sample packets to transmit DSD audio data across the HDMI link to the downstream sink. The ADV8003
supports up to six channels of DSD data which can be input onto six data lines clocked by the signal input to DSD_CLK.
The ADV8003 can be configured to receive a DSD stream by setting
to 0b010. The mode of the DSD stream input to
the ADV8003 can be set via the
field. The audio sampling frequency must be set via the
DSD clock input to SCLK has a frequency that is 64 times the audio sampling frequency programmed in the
field.
Refer to
for additional details on the DSD modes supported by the ADV8003.
Table 61: Valid Configuration for audioif_sf[2:0] Address B8 (Main), Address 0x74[4:2]
audio_input_sel Value
audioif_sf Value Options
Corresponding Configuration
≠0b010
0b000
Not DSD Audio
0b011
0b001
DSD Audio, 64x32 kHz
0b010
DSD Audio, 64x44.1 kHz
0b011
DSD Audio, 64x48 kHz
0b100
DSD Audio, 64x88.2 kHz
0b101
DSD Audio, 64x96 kHz
0b110
DSD Audio, 64x176.4 kHz
0b111
DSD Audio, 64x192 kHz
6.11.2.4.
HBR Audio
The ADV8003 uses an HBR audio packet to transmit across the TMDS link compressed audio streams conforming to IEC 61937 and with
high bit rate (that is, bit rate higher than 6.144 Mbps).
The ADV8003 can be configured to receive an HBR stream by setting
to 0b011. The use of one or four input
stream(s) with or without biphase mark (BPM) encoding can be selected via the
field. Note that an audio master clock
input through the pin MCLK_IN is always required for the BPM encoding modes. For HBR mode, the audio sampling frequency must be
set via the
field.
can be toggled from 0 to 1 to synchronize the Pa and Pb syncword, which marks the beginning of a stream repetition with the
subpacket 0. For data bursts with a repetition period, which is a multiple of four frames, the synchronization will persist. If the data burst
does not have a repetition period of four frames, setting
is not needed but will not have any negative effects. The transition of
the bit from 0 to 1 causes the one time synchronization, so setting the bit from 1 to 0 will have no effect.
Summary of Contents for ADV8003
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